We present an analytical and continuous dc model for cylindrical undoped surrounding-gate (SGT) MOSFETs in which the channel current is written as an explicit function of the applied voltages. The model is based on a new unified charge control model developed for this device. The explicit model shows good agreement with the numerical exact solution obtained from the new charge control model, which was previously validated by comparison with three-dimensional numerical simulations.

Explicit continuous model for long-channel undoped surrounding gate MOSFETs

Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V/sub t/ allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C/sub gc/-V/sub GS/ characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C/sub gc/ characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C/sub gc/ curve can be related to the effective carrier transit time determined using the V/sub GS/ dependent field effect mobility.

Threshold voltage, field effect mobility, and gate-to-channel capacitance in polysilicon TFTs

The transport and recombination of minority carriers in heavily doped emitters plays a crucial role in the performance of silicon bipolar transistors and solar cells. In the past, only order-of-magnitude prediction of the value of the current injected into a heavily doped emitter was possible. The limitations to a more accurate modelling stemmed from: (1) the incomplete understanding of the physics of minority carriers in heavily doped semiconductors; (2) the lack of precise measurements of the relevant material parameters; (3) the difficulties encountered with the modelling of transport and recombination in non-homogeneously doped regions, and (4) problems with the characterization of “real” emitters of bipolar devices. This paper reviews recent experimental and theoretical efforts that addressed some of these issues, with the goal of being able to achieve accurate modelling of the current injected into an arbitrary heavily doped region in a silicon device.

Modelling of minority-carrier transport in heavily doped silicon emitters

Sb2Se3 appeared as a very promising solar absorber because of their attractive material, optical and electrical properties. Previously, we reported thermal evaporated superstrate CdS/Sb2Se3 solar cell achieving 1.9% efficiency. In this letter, we improved device performance to 3.7% (Voc = 0.335 V, Jsc = 24.4 mA/cm2, and FF = 46.8%) by an additional selenization step. Careful external quantum efficiency, capacitance-voltage profiling, and photoresponse study indicated selenization probably compensated selenium loss during thermal evaporation, reducing VSe associated recombination loss and improving device performance.

Selenization of Sb2Se3 absorber layer: An efficient step to improve device performance of CdS/Sb2Se3 solar cells

Sb2Se3 is a very promising absorber material for thin film photovoltaics because of its ideal band gap, strong optical absorption, and non-toxic and earth-abundant constituents. However, only until this year Sb2Se3 solar cell was reported. Here, we present the fabrication and characterization of thermally evaporated superstrate CdS/Sb2Se3 solar cell. Our device achieved a power conversion efficiency of 1.9% (Voc = 300 mV, Jsc = 13.2 mA/cm2, and FF = 48%) and showed good stability. Moreover, using current-voltage measurement, admittance spectroscopy, capacitance-voltage profiling, and drive level capacitance profiling, device characteristics and performance limiting factors are revealed and discussed.

Thermal evaporation and characterization of superstrate CdS/Sb2Se3 solar cells

For quasi-neutral regions of semiconductor devices with position-dependent composition, we have derived expressions for the position dependence of the excess minority-carrier density and for relevant recombination currents To make the development concrete, we study nonuniformly and heavily doped emitter regions of silicon p-n junction devices The expressions developed differ from those previously advanced in that they are in the form of a multiple integral series, yielding, by truncation, many different orders of approximation Correspondences exist between some of the different orders of approximation and various solutions previously obtained All of the mechanisms relating to hole and electron transport in position-dependent heavily doped semiconductors are accounted for in the new expressions These mechanisms include bandgap narrowing, majority-carrier degeneracy, Auger recombination lifetime, etc To assess the accuracy of the various orders of approximation, we compare their predictions with a numerical solution We determine that the simplest approximation, which contains only one term of the integral series, is accurate to within about 5 percent of the numerical solution for thin emitters (∼02 µm) provided the surface recombination velocity is less than 105cm/s It thus applies directly to bipolar transistors with polysilicon contacts, and to surface-passivated solar cells This new solution, which we call the zeroth-order or quasi-neutral quasi-equilibrium approximation, is simpler than solutions previously put forward If the emitter junction is deep or the contact is ohmic, the higher-order approximations provide whatever accuracy is needed We separate the emitter recombination current into charge and a characteristic time, enabling the calculation of the contribution of emitter to capacitance and to delay in the time domain or phase shift in the frequency domain

Systematic analytical solutions for minority-carrier transport in semiconductors with position-dependent composition, with application to heavily doped silicon

A comprehensive analytical model for the quasi-static capacitance of the space-charge region of p-n junction devices is presented. It describes the capacitance for all voltages, including voltages large enough to cause the junction barrier to vanish. The model applies for exponential-constant doping profiles, the limiting cases of which are the step and the linear-graded profiles. In addition to the analytical model, an iterative technique is developed to yield numerically the thickness of the space-charge region as a function of voltage. The capacitance model shows good agreement when compared with measured dependencies, With an empirical model for circuit simulation, and with models based on device simulation. The model extends previous replacements of the depletion capacitance, provides a tool for circuit simulation, and is intended to provide understanding of the physics related to storage of mobile holes and electrons in the junction space-charge region.

Forward-voltage capacitance and thickness of p-n junction space-charge regions

New DC methods to measure the collector resistance R/sub C/ and emitter resistance R/sub E/ are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R/sub C/. R/sub E/ is obtained from the measured lateral portion of R/sub C/ and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R/sub C/ on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R/sub C/ is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R/sub E/ a value for the specific contact resistance for the polysilicon emitter contact of rho /sub c/ equivalent to 50 Omega - mu m/sup 2/ is obtained. >

Measurement of collector and emitter resistances in bipolar transistors

Novel methods for parameter extraction for bipolar transistors are presented. Emphasis is placed on reliable measurements of small-size transistors, examples are shown for Si integrated circuit transistors with emitters smaller than 10 mu m/sup 2/. Advantages over measurements on large-area test devices are discussed. Parameters measured are the current-dependent base and emitter series resistances, emitter contact resistance, base-emitter and base-collector space-charge region capacitances, junction temperature, and base and collector saturation currents. Applications to heterojunction bipolar transistors are demonstrated. >

Parameter extraction for bipolar transistors

A simple and efficient one-dimensional numerical technique is presented that determines the small-signal minority-carrier transport in the quasineutral regions of bipolar devices, such as diodes and transistors, under sinusoidal excitation. The technique is applied to study small-signal properties of p-n junction diodes and bipolar transistors. Examples treated include the frequency dependence of transistor current gain, the diffusion capacitance of a quasineutral base or emitter, and base-layer carrier propagation delay. >

J.-S. Park

Papers

Systematic analytical solutions for minority-carrier transport in semiconductors with position-dependent composition, with application to heavily doped silicon

Forward-voltage capacitance and thickness of p-n junction space-charge regions

Measurement of collector and emitter resistances in bipolar transistors

Parameter extraction for bipolar transistors

Numerical analysis and interpretation of the small-signal minority-carrier transport in bipolar devices