Showing papers by "Jack T. Kavalieros published in 2017"

Charge trap layer in back-gated thin-film transistors

Abstract: A back-gated thin-film transistor (TFT) includes a gate electrode, a gate dielectric on the gate electrode, an active layer on the gate dielectric and having source and drain regions and a semiconductor region physically connecting the source and drain regions, a capping layer on the semiconductor region, and a charge trap layer on the capping layer. In an embodiment, a memory cell includes this back-gated TFT and a capacitor, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline, the capacitor having a first terminal electrically connected to the drain region, a second terminal, and a dielectric medium electrically separating the first and second terminals. In another embodiment, an embedded memory includes wordlines extending in a first direction, bitlines extending in a second direction crossing the first direction, and several such memory cells at crossing regions of the wordlines and bitlines.

Encapsulation layers of thin film transistors

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area Other embodiments may be described and/or claimed

Non-planar gate all-around device and manufacturing method thereof

Abstract: The invention discloses a non-planar gate all-around device and a manufacturing method thereof. In one embodiment, the device comprises a substrate, and the substrate is provided with a top surface with a first lattice constant. An embedded epitaxial source electrode area and an embedded epitaxial drain electrode area are formed on the top surface of the substrate. The embedded epitaxial source electrode area and the embedded epitaxial drain electrode area have a second lattice constant different from the first lattice constant. Channel nanowires with a third lattice constant are formed between the embedded epitaxial source electrode area and the embedded epitaxial drain electrode area, and are coupled with the embedded epitaxial source electrode area and the embedded epitaxial drain electrode area. In another embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. The channel nanowires comprise a bottommost channel nanowire, and a bottom gate isolator is formed on the top surface of the substrate below the bottommost channel nanowire. Gate dielectric layers are formed on and around each channel nanowire. Gate electrodes are formed on the gate dielectric layers, and enclose each channel nanowire.

Germanium-rich channel transistors including one or more dopant diffusion barrier elements

Abstract: Techniques are disclosed for forming germanium (Ge)-rich channel transistors including one or more dopant diffusion barrier elements The introduction of one or more dopant diffusion elements into at least a portion of a given source/drain (S/D) region helps inhibit the undesired diffusion of dopant (eg, B, P, or As) into the adjacent Ge-rich channel region In some embodiments, the elements that may be included in a given S/D region to help prevent the undesired dopant diffusion include at least one of tin and relatively high silicon Further, in some such embodiments, carbon may also be included to help prevent the undesired dopant diffusion In some embodiments, the one or more dopant diffusion barrier elements may be included in an interfacial layer between a given S/D region and the Ge-rich channel region and/or throughout at least a majority of a given S/D region Numerous embodiments, configurations, and variations will be apparent

Tri-gate device and manufacturing method

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a semiconductor body having a top surface and sidewalls on both right and left sides formed on a substrate, and to provide a method for manufacturing the semiconductor device.SOLUTION: A gate dielectric layer is formed on a top surface of a semiconductor body and on sidewalls on both right and left sides of the semiconductor body. A gate electrode is formed on a gate dielectric on the top surface of the semiconductor body and is formed adjacently to the gate dielectric on the sidewalls on both the right and left sides of the semiconductor body.SELECTED DRAWING: Figure 3

Semiconductor devices and fabricating methods thereof using selectively regrown top contact

Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Iii-v gaa deep gate-all-around semiconductor device having germanium or group iii-v active layer

Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.

High-voltage field effect transistor

Abstract: The invention discloses a transistor suitable for high-voltage and high-frequency operation, especially a high-voltage field effect transistor. A substrate is vertically or horizontally provided with a nano wire. The longitudinal length of the nano wire is limited in a trench region of a first semiconductor material, and a source electrode region is electrically coupled to a first end of a trench region. A drain electrode region is electrically coupled to a second end of the trench region, and an extrinsic drain electrode region is disposed between the trench region and the drain electrode region. A band gap of the extrinsic drain electrode region is wider than a band gap of the first semiconductor. A grid stacked boy comprising a grid conductor and a grid insulator completely winds around the trench region in a coaxial manner. Similarly, the drain electrode and the source electrode completely wind around the drain electrode region and the source electrode region in a coaxial manner.

CMOS implementation of Germanium, III-V nano-wires and nano-belts in grid-wound framework

Abstract: Disclosed are a common integrated framework and technology for heterogeneous materials such as III-V family semiconductor materials and IV-family semiconductors (such as Ge) on the same substrate (such as silicon). According to CMOS implementation of Germanium, III-V nano-wires and nano-belts in the grid-wound framework, a multi-layer heterogeneous semiconductor material stacked body with the alternating nano-wires and sacrificial layers are used for releasing the nano-wires and allow the formation of a coaxial grid structure of a channel region fully around a nano-wire transistor; single PMOS and NMOS channel semiconductor materials are integrated with a starting substrate of a covering layer with an alternating GE/III-V layer; vertical integration of multiple stacked nano-wires in a single PMOS device and a single NMOS device provides considerable driving currents in a given layout area.

A semiconductor device and a method of fabricating a semiconductor device

Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Defect-free device manufacturing on the basis of rib in cross epitaxial overgrowth area

Abstract: FIELD: physics.SUBSTANCE: electronic device ribs are formed by the epitaxial growth of the first material layer over the substrate surface at the gap bottom formed between the side walls of the shallow trench isolation (STI) areas. The trench height may be, at least, 1.5 of its width size, and the first layer may fill less than the trench height. Then, the second material layer may be epitaxially grown on the first trench layer and over the upper surfaces of the STI areas. The second layer may have the second width extending over the tench and over the upper surface portions of the STI areas. The second layer may then be structured and etched to form a pair of the electronic device ribs over the upper surface portions of the STI areas, proximally to the trench.EFFECT: invention makes it possible to eliminate crystal defects in the ribs, because of the difference between the constants of the crystal lattices at the boundary of the layer transition.20 cl, 10 dwg

Transistor with wide bandgap channel and narrow bandgap source/drain

Abstract: An electronic device comprises a first layer on a buffer layer on a substrate. A source/drain region is deposited on the buffer layer. The first layer comprises a first semiconductor. The source/drain region comprises a second semiconductor. The second semiconductor has a bandgap that is smaller than a bandgap of the first semiconductor. A gate electrode is deposited on the first layer.

Doped insulator cap to reduce source/drain diffusion for germanium nmos transistors

Abstract: Integrated circuit transistor structures are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent insulator regions during fabrication. The n-MOS transistor device may include at least 75% germanium by atomic percentage. In an example embodiment, a dopant-rich insulator cap is deposited adjacent to the source and/or drain regions, to provide dopant diffusion reduction. In some embodiments, the dopant-rich insulator cap is doped with an n-type impurity including Phosphorous in a concentration between 1 and 10 % by atomic percentage. In some embodiments, the dopant-rich insulator cap may have a thickness in the range of 10 to 100 nanometers and a height in the range of 10 to 200 nanometers.

Sb-Basierte CMOS-Vorrichtungen

Abstract: Eine CMOS-Vorrichtung aus Material der Gruppe III–V kann NMOS- und PMOS-Abschnitte aufweisen, die uber mehrere ihrer Schichten hinweg im wesentlichen gleich sind. Dies kann es erleichtern, die CMOS-Vorrichtung herzustellen und Abweichungen der Warmeausdehnungskoffizienten zwischen den NMOS- und PMOS-Abschnitten zu vermeiden.

Electronic device fin, method to form an electronic device fin and system having an electronic device fin for computing

Abstract: A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the tin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.