G
G. Curello
Researcher at Intel
Publications - Â 11
Citations - Â 723
G. Curello is an academic researcher from Intel. The author has contributed to research in topics: Transistor & NMOS logic. The author has an hindex of 9, co-authored 11 publications receiving 692 citations.
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Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Proceedings ArticleDOI
A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
C.-H. Jan,M. Agostinelli,M. Buehler,Zhanping Chen,S.-J. Choi,G. Curello,H. Deshpande,S. Gannavaram,Hafez Walid M,U. Jalan,M. Kang,Pramod Kolar,K. Komeyli,B. Landau,A. Lake,N. Lazo,Seung Hwan Lee,T. Leo,J. Lin,Nick Lindert,S. Ma,L. McGill,C. Meining,A. Paliwal,Joodong Park,K. Phoa,Ian R. Post,N. Pradhan,M. Prince,Abdur Rahman,J. Rizk,L. Rockford,G. Sacks,A. Schmitz,H. Tashiro,Curtis Tsai,P. Vandervoorn,J. Xu,L. Yang,J.-Y. Yeh,J. Yip,Kevin Zhang,Yuegang Zhang,P. Bai +43 more
TL;DR: The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently.
Proceedings ArticleDOI
An advanced low power, high performance, strained channel 65nm technology
S. Tyagi,C. Auth,P. Bai,G. Curello,H. Deshpande,S. Gannavaram,Oleg Golonzka,R. Heussner,R. James,C. Kenyon,Seok-Hee Lee,Nick Lindert,Mark Y. Liu,Ramune Nagisetty,Sanjay Natarajan,C. Parker,J. Sebastian,Sell Bernhard,Swaminathan Sivakumar,A. St. Amour,K. Tone +20 more
TL;DR: In this article, an advanced low power, strained channel, dual poly CMOS 65nm technology with enhanced transistor performance is presented at 1V and off current of 100nA/mum.
Proceedings ArticleDOI
A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors
Chia-Hong Jan,P. Bai,J. Choi,G. Curello,S. Jacobs,J. Jeong,K. Johnson,D. Jones,S. Klopcic,J. Lin,Nick Lindert,A. Lio,Sanjay Natarajan,J. Neirynck,P. Packan,Joodong Park,Ian R. Post,M. Patel,S. Ramey,P. Reese,L. Rockford,A. Roskowski,G. Sacks,B. Turkot,Yih Wang,Liqiong Wei,J. Yip,Ian A. Young,Kevin Zhang,Yuegang Zhang,M. Bohr,B. Holt +31 more
TL;DR: In this article, a leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products, achieving record PMOS/NMOS drive currents of 038/066 mA/mum, respectively, at 12V and off-state leakage of 100 pA /mum.
Proceedings ArticleDOI
A 65nm CMOS SOC Technology Featuring Strained Silicon Transistors for RF Applications
Ian R. Post,Muhammad Akbar,G. Curello,S. Gannavaram,Hafez Walid M,U. Jalan,K. Komeyli,J. Lin,Nick Lindert,Joodong Park,J. Rizk,G. Sacks,C. Tsai,D. Yeh,P. Bai,C.-H. Jan +15 more
TL;DR: In this article, a 65nm CMOS technology (29nm Lgate, 210nm pitch) employing uni-axial strained silicon transistors was used to achieve record-breaking performance with fT/fMAX values of 238 GHz/295 GHz.