With the growth of high performance computing on many industrial sectors that includes mobile/network and data centers/servers, the need for continued technology scaling and advancements on new process technology have paved ways to manufacture advanced semiconductor products. High-k + Metal gate devices and most recently EUV lithography process have become a key enabler for the 7nm technology nodes and beyond [1]. These technologies are being adopted in the advanced DRAM nodes. DRAM memory uses various devices such as MOSFETs (w/ and w/o HK+MG), cell transistor, cell capacitor, and its reliability has also been considered according to the designed purposes. This paper reviews comprehensive reliability on all types of devices used at each circuit in 15nm DRAM memory. The intrinsic reliability of devices in peripheral regions was guaranteed with systematic wafer-level-reliability evaluation up to product level testing for 1000hrs. The reliability of transistors in core regions was verified using design for reliability, various test structures, and up to an accelerated product level aging test. With the suggested degradation modeling of the capacitor in cell regions, the result on 32GB DIMM field tested for over 1 years shows the best in class reliability results and meets 10yrs of lifetime.

Transistor Reliability Characterization for Advanced DRAM with HK+MG & EUV process technology

AbstractRecently, we are witnessing a surge in DRAM-based Processing in Memory (PIM) publications from academia and industry. The architectures and design techniques proposed in these publications vary largely, ranging from integration of computation units in the DRAM IO region (i.e., without modifying DRAM core circuits) to modifying the highly optimized DRAM sub-arrays inside the banks for computation operations. Additionally, the underlying memory type, e.g., DDR4, LPDDR4, GDDR6 and HBM2, for DRAM-PIM is also different. This paper presents the assessment of DRAM-PIM architectural design decisions adapted in all DRAM-PIM publications. Our study presents an in-depth analysis of computation unit placement location, i.e., from the chip-level down to DRAM sub-array-level, and discusses the implementation challenges for a computation unit in various regions of commodity DRAM architectures. We also elaborate on the architectural bottlenecks associated with the scalability of DRAM-PIM performance and energy gains, and present architectural approaches to address the issues. Finally, our assessment covers other important design dimensions, such as computation data formats and DRAM-PIM memory controller design.KeywordsProcessing-in-MemoryPIMDRAMCNNDNN 

A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions

Mobile systems for 5G communications and emerging technologies, such as advanced driver assistance system (ADAS), augmented reality (AR), and artificial intelligence (AI), demand high-density, high-speed, and low-power DRAM.LPDDR5 has played an important role in such systems, by offering continuous improvements in memory density (8, 12, and 16Gb) and speed (up to 8.5Gb/s) [1, 2, 3].LPDDR5X has new high-speed enabling features: per-pin DFE training, pre-emphasis for DQ driver, receiver offset calibration training, and a read duty-cycle adjuster. By employing these speed enhancement techniques, we have successfully implemented a 9.5Gb/s/pin 16Gb LPDDR5X using a fourth generation 10nm DRAM fabrication technology. This paper also presents a power-efficient LPDDR5X using (1) a non-stacking bank architecture, (2) an offset-calibrated sense amplifier for the global data lines, (3) an extended dynamic voltage and frequency scaling core (DVFSC), (4) a stacked output driver, and (5) a low-power data aligner. 

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

With the growth of high performance computing on many industrial sectors that includes mobile/network and data centers/servers, the need for continued technology scaling and advancements on new process technology have paved ways to manufacture advanced semiconductor products. High-k + Metal gate devices and most recently EUV lithography process have become a key enabler for the 7nm technology nodes and beyond [1]. These technologies are being adopted in the advanced DRAM nodes. DRAM memory uses various devices such as MOSFETs (w/ and w/o HK+MG), cell transistor, cell capacitor, and its reliability has also been considered according to the designed purposes. This paper reviews comprehensive reliability on all types of devices used at each circuit in 15nm DRAM memory. The intrinsic reliability of devices in peripheral regions was guaranteed with systematic wafer-level-reliability evaluation up to product level testing for 1000hrs. The reliability of transistors in core regions was verified using design for reliability, various test structures, and up to an accelerated product level aging test. With the suggested degradation modeling of the capacitor in cell regions, the result on 32GB DIMM field tested for over 1 years shows the best in class reliability results and meets 10yrs of lifetime. 

Transistor Reliability Characterization for Advanced DRAM with HK+MG &amp; EUV process technology

An asymmetrically controlled sense amplifier with boosted sensing voltage difference for low-voltage and high-density DRAM

The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA. In this work, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size. Additionally, the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier (SA) with dedicated VREFs for a 1-tap DFE. The side effect of a mosaic architecture is the performance of the internal DRAM due to a 1.64× long bus line; however, this is mitigated by a fully-source-synchronous (FSS) bus scheme that is robust to PVT variation. In addition, to reduce the power consumption of the long bus line a low-level swing (LLS) scheme is used in low frequency mode. Furthermore, to enhance power efficiency and yield an adaptive-body-bias (ABB) scheme is introduced in a 3rd generation of a 10nm DRAM process.

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM

Jae-Woo Lee

Papers

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM