scispace - formally typeset
D

Dongkeon Lee

Researcher at Samsung

Publications -  8
Citations -  71

Dongkeon Lee is an academic researcher from Samsung. The author has contributed to research in topics: Dram & Signal. The author has an hindex of 3, co-authored 7 publications receiving 31 citations. Previous affiliations of Dongkeon Lee include Sungkyunkwan University.

Papers
More filters
Journal ArticleDOI

Tob is a potential marker gene for the basal layer of the epidermis and is stably expressed in human primary keratinocytes

Park Gibeyong, +6 more
- 01 Mar 2006 - 
TL;DR: This work investigated the expression pattern of Tob gene product to understand the possible role in differentiation of keratinocytes and epidermis.
Proceedings ArticleDOI

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM

Yong-Hun Kim, +33 more
TL;DR: In this article, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size, and the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier with dedicated Vthis articles for a 1-tap DFE.
Proceedings ArticleDOI

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Kyung-Soo Ha, +29 more
TL;DR: This paper presents a 1st generation 10nm-class process LPDDR5, which includes novel schemes that increase the maximum bandwidth, such as WCK clocking and non-target ODT (NT-ODT) and power consumption is reduced by low power schemes.
Proceedings ArticleDOI

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

Hyung-Joon Chi, +38 more
TL;DR: A 8,5Gb/s 12Gb LPDDR5 with a hybrid bank architecture (split/merged bank), a skew-tolerant scheme, bus-based ROBI AC, and speed-boosting techniques based on 2nd generation 10nm DRAM process are proposed.
Journal ArticleDOI

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

Kyung-Soo Ha, +16 more
- 01 Jan 2020 - 
TL;DR: To increase data rate, a WCK clocking scheme that is less vulnerable to power noise is adopted and a non-target ODT mode is proposed to reduce reflection noise in a two-rank system and to reduce self-refresh power, a couple of techniques are proposed for saving power.