Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption However, the increased severity of manufacturing-induced parameter variations at lower voltages limits voltage scaling to a minimum voltage, Vccmin, below which a processor cannot operate reliably Memory cell failures in large memory structures (eg, caches) typically determine the Vccmin for the whole processor Memory failures can be persistent (ie, failures at time zero which cause yield loss) or non-persistent (eg, soft errors or erratic bit failures) Both types of failures increase as supply voltage decreases and both need to be addressed to achieve reliable operation at low voltages In this paper, we propose a novel adaptive technique to improve cache lifetime reliability and enable low voltage operation This technique, multi-bit segmented ECC (MS-ECC) addresses both persistent and non-persistent failures Like previous work on mitigating persistent failures, MS-ECC trades off cache capacity for lower voltages However, unlike previous schemes, MS-ECC does not rely on testing to identify and isolate defective bits, and therefore enables error tolerance for non-persistent failures like erratic bits and soft errors at low voltages Furthermore, MS-ECC's design can allow the operating system to adaptively change the cache size and ECC capability to adjust to system operating conditions Compared to current designs with single-bit correction, the most aggressive implementation for MS-ECC enables a 30% reduction in supply voltage, reducing power by 71% and energy per instruction by 42%

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Improving cache lifetime reliability at ultra-low voltages

4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single circuit by eliminating the feedback path of a conventional DBI AC circuit while achieving high-speed operation. The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay. Ronmiddot tuning further improves the voltage and time margin by adding a user-supplied offset to auto-calibrated Ronmiddot. In addition, a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs. Measured results show that DBI DC coding reduces the peak-to-peak jitter from 65.5 ps to 44.5 ps and the voltage fluctuation from 183 mV to 115 mV at the data rate of 4 Gb/s with the 2 V.

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

Data bus inversion apparatus, systems, and methods

The performance/energy trade-off is widely acknowledged as a primary design consideration for modern processors. A less discussed, though equally important, trade-off is the reliability/energy trade-off. Many design features that increase reliability (e.g., redundancy, error detection, and correction) have the side effect of consuming more energy. Many energy-saving features (e.g., voltage scaling) have the side effect of making systems less reliable. In this paper, we propose an adaptive cache design that enables the operating system to optimize for performance or energy efficiency without sacrificing reliability. Our proposed mechanism enables a cache with a wide operating range, where the cache can use a variable part of its data array to store error-correcting codes. A reliable, energy-efficient cache can use up to half of its data array to store error-correcting codes so that it can reliably operate at a low voltage to reduce energy. A reliable high-performance cache uses its whole data array, but operates at a higher voltage to improve reliability while sacrificing energy. We propose a hardware mechanism that allows the operating system to choose different points within that operating range based on the desired levels of performance, energy, and reliability.

Adaptive Cache Design to Enable Reliable Low-Voltage Operation

The authors of the above titled article (ibid., vol. 44, no. 8, pp. 2222-2232, Aug. 09) acknowledge the contribution from an earlier paper.

Correction on “A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme” [Aug 09 2222-2232]

A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21 ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance.

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA. In this work, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size. Additionally, the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier (SA) with dedicated VREFs for a 1-tap DFE. The side effect of a mosaic architecture is the performance of the internal DRAM due to a 1.64× long bus line; however, this is mitigated by a fully-source-synchronous (FSS) bus scheme that is robust to PVT variation. In addition, to reduce the power consumption of the long bus line a low-level swing (LLS) scheme is used in low frequency mode. Furthermore, to enhance power efficiency and yield an adaptive-body-bias (ABB) scheme is introduced in a 3rd generation of a 10nm DRAM process.

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM

As the automotive and AI industries are expanding rapidly, global-shutter (GS) image sensors are playing a more significant role in the perception system. More specifically, GS image sensors are required in various fields involving IR, including the face-ID in mobile devices, the driver monitoring system in automotive applications, and factory automation. GS image sensors are necessary for these applications because they can capture freeze-frame images without motion distortion due to their advantage in the pixel operation method. The simultaneous pixel exposure and in-pixel storing capability allow GS image sensors to achieve high-quality imaging, while the sequential pixel exposure and readout of rolling-shutter (RS) image sensors results in image distortion known as the jello effect. For mobile and automotive applications, a small form factor while maintaining a low parasitic light sensitivity (PLS) and low noise is crucial. In conventional backside illuminated (BSI) charge-domain GS image sensors, a light-shielding structure over the storage area must be formed in order to suppress the influence of parasitic light during the readout operation. Therefore, the introduction of such a light-shielding structure reduces the effective photodiode area, which results in a loss of full-well capacity (FWC), light sensitivity of the sensor, and pixel scalability.

5.5 A 2.1e − Temporal Noise and −105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology

Jinyong Choi

Papers

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM

5.5 A 2.1e − Temporal Noise and −105dB Parasitic Light Sensitivity Backside-Illuminated 2.3µm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology