This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm2, including calibration.

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

This paper presents a dual-loop two-step ZQ calibration scheme with a 20-nm DRAM process to support dedicated supply voltages ( $V_{DD}$ and $V_{DDQ}$ ). The proposed calibration scheme improves system signal integrity by maintaining the targeted output level ( $V_{\mathrm {OH}}$ ) in dynamic voltage–frequency scaling (DVFS) function, where $V_{DD}$ and $V_{DDQ}$ can be independently controlled to save system power. A two-step conversion algorithm alleviates the increase in calibration time, which is caused by an additional on-die termination (ODT) calibration for command/address (CA). The offset of a dynamic comparator in a ZQ calibration engine is averaged by a fraction-referred input switching-then-averaging (FISA) scheme which minimizes the effect of kickback noise. A code-referred periodic ZQ update (CPZU) scheme tracks the voltage and temperature variation during the background mode while minimizing the chance of malfunction by interference of both DRAM internal noise and external power noise. By applying the DVFS function based on the device usage by the user scenario in this design ( $V_{DD} =1.1$ V and $V_{DDQ} = 0.95$ V) at 1.6 Gbps, the read and the write operating power consumption can be saved by 17.7% and 18.2%, respectively, without a dynamic drop in performance. Therefore, the proposed dual-loop two-step ZQ calibration design improves the overall DRAM power efficiency based on the existing LPDDR4 SDRAM architecture without circuit overhead.

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

An 8.5-Gb/s/pin (Gb/s) 12-Gb LPDDR5 SDRAM is implemented in a second-generation 10-nm DRAM process with a hybrid-bank architecture that provides a power-optimized bank solution depending on the bank modes (4B/4BG, 16B-merged bank, 8B-split bank). Based on the specified bank modes, vertical and horizontal skew-cancel schemes for high density and an RBUS-based DBI ac to minimize data transition are newly proposed. Thus, the switching power of RBUS DBI ac is saved by 8.9% compared to that of DBI ac “OFF.” To improve the rank interleaving efficiency with a current increase, partially enabled WCK (PE-WCK) mode is proposed, which minimizes the number of enabled circuits for maintaining the WCK2CK synchronization. Therefore, the current can be saved by 62% without a timing constraint compared to the WCK always-ON mode. To achieve high-speed operation beyond 6.4 Gb/s, speed-boosting techniques, namely, the two-step duty corrector, active resonant load (ARL), and one-tap decision feedback equalizer (DFE) with offset calibration, are newly adopted. In the coarse step in the two-step duty corrector, the value of the duty error decreases to below 5% by suppressing the dc signal. In the fine step, the remaining duty error is further reduced within 2.5 ps by the duty cycle monitor (DCM) and duty cycle adjustor (DCA). Moreover, the skew increase beyond 6.4 Gb/s due to the bandwidth limit by the heavy loading of four-phase WCK signals is alleviated by the ARL, where the four-phase skew is within 5 ps irrespective of process, voltage, and temperature (PVT) variations. The direct feedback DFE enables fast feedback (< 118 ps) for tap coefficient control, and offset calibration reduces the three-sigma offset of the four dynamic latches in DQ within 5 mV.

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques

With the growth of high performance computing on many industrial sectors that includes mobile/network and data centers/servers, the need for continued technology scaling and advancements on new process technology have paved ways to manufacture advanced semiconductor products. High-k + Metal gate devices and most recently EUV lithography process have become a key enabler for the 7nm technology nodes and beyond [1]. These technologies are being adopted in the advanced DRAM nodes. DRAM memory uses various devices such as MOSFETs (w/ and w/o HK+MG), cell transistor, cell capacitor, and its reliability has also been considered according to the designed purposes. This paper reviews comprehensive reliability on all types of devices used at each circuit in 15nm DRAM memory. The intrinsic reliability of devices in peripheral regions was guaranteed with systematic wafer-level-reliability evaluation up to product level testing for 1000hrs. The reliability of transistors in core regions was verified using design for reliability, various test structures, and up to an accelerated product level aging test. With the suggested degradation modeling of the capacitor in cell regions, the result on 32GB DIMM field tested for over 1 years shows the best in class reliability results and meets 10yrs of lifetime.

Transistor Reliability Characterization for Advanced DRAM with HK+MG & EUV process technology

AbstractRecently, we are witnessing a surge in DRAM-based Processing in Memory (PIM) publications from academia and industry. The architectures and design techniques proposed in these publications vary largely, ranging from integration of computation units in the DRAM IO region (i.e., without modifying DRAM core circuits) to modifying the highly optimized DRAM sub-arrays inside the banks for computation operations. Additionally, the underlying memory type, e.g., DDR4, LPDDR4, GDDR6 and HBM2, for DRAM-PIM is also different. This paper presents the assessment of DRAM-PIM architectural design decisions adapted in all DRAM-PIM publications. Our study presents an in-depth analysis of computation unit placement location, i.e., from the chip-level down to DRAM sub-array-level, and discusses the implementation challenges for a computation unit in various regions of commodity DRAM architectures. We also elaborate on the architectural bottlenecks associated with the scalability of DRAM-PIM performance and energy gains, and present architectural approaches to address the issues. Finally, our assessment covers other important design dimensions, such as computation data formats and DRAM-PIM memory controller design.KeywordsProcessing-in-MemoryPIMDRAMCNNDNN 

A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions

The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA. In this work, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size. Additionally, the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier (SA) with dedicated VREFs for a 1-tap DFE. The side effect of a mosaic architecture is the performance of the internal DRAM due to a 1.64× long bus line; however, this is mitigated by a fully-source-synchronous (FSS) bus scheme that is robust to PVT variation. In addition, to reduce the power consumption of the long bus line a low-level swing (LLS) scheme is used in low frequency mode. Furthermore, to enhance power efficiency and yield an adaptive-body-bias (ABB) scheme is introduced in a 3rd generation of a 10nm DRAM process.

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM

This paper presents a dual-loop 2-step ZQ calibration scheme with 20nm DRAM process to support dedicated supply voltage (VDD, VDDQ). The proposed calibration scheme maintains a target value of on-die termination (ODT) in DQ/CA regardless of the supply-voltage variations which are caused by dynamic voltage frequency switching (DVFS) and alleviates the calibration time which is increased by insertion of additional CA calibration. The offset of a comparator is averaged out by fraction-referred input switching-then-averaging scheme (FISA). And code-referred periodic ZQ update (CPZU) scheme can track the VT variation while minimizing the interference.

Si-Hyeong Cho

Papers

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3 rd -Generation 10nm DRAM

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM