In this study, the resistive switching and synaptic properties of a complementary metal-oxide semiconductor-compatible Ti/a-BN/Si device are investigated for neuromorphic systems. A gradual change ...

Synaptic Characteristics of Amorphous Boron Nitride-Based Memristors on a Highly Doped Silicon Substrate for Neuromorphic Engineering.

Recent progress on two-dimensional neuromorphic devices and artificial neural network

A silicon nanowire field effect transistor (FET) straddled by the double-gate was demonstrated for biosensor application. The separated double-gates, G1 (primary) and G2 (secondary), allow independent voltage control to modulate channel potential. Therefore, the detection sensitivity was enhanced by the use of G2. By applying weakly positive bias to G2, the sensing window was significantly broadened compared to the case of employing G1 only, which is nominally used in conventional nanowire FET-based biosensors. The charge effect arising from biomolecules was also analyzed. Double-gate nanowire FET can pave the way for an electrically working biosensor without a labeling process.

Double-gate nanowire field effect transistor for a biosensor = Double-Gate 구조의 나노와이어 트랜지스터와 바이오센서 응용에 대한 연구

In this article, an L-shaped tunnel field-effect transistor (LTFET)-based one-transistor dynamic random access memory (1T DRAM) with SiGe storage region was demonstrated through 2-D TCAD simulations. The SiGe storage is utilized to boost not only the sense margin (SM) but also the retention time (RT) in comparison to the previously published TFET-based 1T DRAMs. The simulation results reveal that the LTFET 1T DRAM acquired the SM of $6.2~\mu \text{A}/\mu \text{m}$ with RT of 1.7 s when 50-nm gate length was adopted at 27 °C, whereas at 85 °C, the LTFET 1T DRAM attains the SM and RT of $5.1~\mu \text{A}/\mu \text{m}$ and 290 ms, respectively. Furthermore, the LTFET 1T DRAM still attains the RT of 1.3 s at 27 °C when the gate length is scaled down to 20 nm. Thus, LTFET 1T DRAM exhibits a better gate length scalability in comparison to the counterpart TFET-based 1T DRAMs. In addition, we observed that the impact of ion irradiation on the proposed cell exhibits almost the same SM before and after the ion strike.

L-Shaped Tunnel Field-Effect Transistor-Based 1T DRAM With Improved Read Current Ratio, Retention Time, and Sense Margin

In this work, a double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time ( ${T}_{\text {ret}}$ ) and larger sensing margin (SM). The designed 1T DRAM achieves ${T}_{\text {ret}} \sim {330}$ and $\sim 200$ ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write “1”) and energy ( $2.16\times 10^{-15}$ J for read “1” and $1.5\times 10^{-17}$ J for read “0” operations). Furthermore, it is revealed that low- $\kappa $ spacer has an effect of increasing ${T}_{\text {ret}}$ in the device.

Performance Improvement of 1T DRAM by Raised Source and Drain Engineering

In this article, a double-gate (DG) junctionless (JL) transistor with physical barriers is proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this topology, the holes are stored in the region blocked by physical barriers constructed by oxides underneath the source and drain regions rather than a potential well formed by n+-p-n+ as in the conventional structures. The proposed topology achieves an elongated retention time ( ${T}_{\text {ret}}$ ) with larger physical barrier thickness ( ${T}_{\text {oxPB}}$ ) and wider barrier offset length ( ${L}_{\text {BO}}$ ) due to a reduction in band-to-band tunneling (BTBT) (during hold “0”) and recombination (during hold “1”). Maximum retention times of ~2.5 s and ~33 ms have been achieved for channel doping of 1019 cm−3 at 27 °C and 85 °C, respectively, with gate length ( ${L}_{g}$ ) of 100 nm at small drain bias ( ${V}_{\text {DS}}$ ) of 1 V during write “1.” Results demonstrate a better gate length scalability and a retention time of ~4 ms at ${L}_{g}$ of 15 nm with thinner Si channel thickness under the gate ( ${T}_{\text {Si}}$ ) and thicker ${T}_{\text {oxPB}}$ . In addition, the effect of temperature on retention time has been analyzed. With optimized ${T}_{\text {oxPB}}$ at ${L}_{g} = {100}$ nm, the retention time decreases due to thermal generation and recombination from ~2.5 s at 27 °C to ~3 ms at 125 °C.

Double-Gate Junctionless 1T DRAM With Physical Barriers for Retention Improvement

In this work, a study on a semi-floating-gate synaptic transistor (SFGST) is performed to verify its feasibility in the more energy-efficient hardware-driven neuromorphic system. To realize short- and long-term potentiation (STP/LTP) in the SFGST, a poly-Si semi-floating gate (SFG) and a SiN charge-trap layer are utilized, respectively. When an adequate number of holes are accumulated in the SFG, they are injected into the nitride charge-trap layer by the Fowler⁻Nordheim tunneling mechanism. Moreover, since the SFG is charged by an embedded tunneling field-effect transistor existing between the channel and the drain junction when the post-synaptic spike occurs after the pre-synaptic spike, and vice versa, the SFG is discharged by the diode when the post-synaptic spike takes place before the pre-synaptic spike. This indicates that the SFGST can attain STP/LTP and spike-timing-dependent plasticity behaviors. These characteristics of the SFGST in the highly miniaturized transistor structure can contribute to the neuromorphic chip such that the total system may operate as fast as the human brain with low power consumption and high integration density.

https://www.mdpi.com/2072-666X/10/1/32/pdf

Design and Characterization of Semi-Floating-Gate Synaptic Transistor

In this article, we report a method for recovering a resistive-switching random access memory (RRAM) from the reset breakdown and enhancing the endurance characteristics. A SiN x -based RRAM device has been fabricated and its switching characteristics are analyzed with a particular interest in reset breakdown. It has been found that the SiN x RRAM in permanent reset breakdown can be revived to high-resistance state (HRS) by thermal recovery, a low-temperature annealing method. The memory window could be widened even with enhanced reset stability and conductance distribution. Temperature-dependent conductance change has been measured in order to figure out the substantial component of conductive filament and the mechanism of thermal recovery. The experimental evidences show that the reset breakdown process is the result of unwanted Si dangling bond (Si-DB) formation. By thermal recovery, Ni filament could be ruptured without applying a high electric field which induces negative set.

Jae Yoon Lee

Papers

Double-Gate Junctionless 1T DRAM With Physical Barriers for Retention Improvement

Design and Characterization of Semi-Floating-Gate Synaptic Transistor

Investigation of the Thermal Recovery From Reset Breakdown of a SiN x -Based RRAM

Investigation of Modified 1T DRAM with Twin Gate Tunneling Field Effect Transistor for Improved Retention Characteristics

Investigation and Optimization of Double-gate MPI 1T DRAM with Gate-induced Drain Leakage Operation