The field of plasma etching is reviewed. Plasma etching, a revolutionary extension of the technique of physical sputtering, was introduced to integrated circuit manufacturing as early as the mid 1960s and more widely in the early 1970s, in an effort to reduce liquid waste disposal in manufacturing and achieve selectivities that were difficult to obtain with wet chemistry. Quickly, the ability to anisotropically etch silicon, aluminum, and silicon dioxide in plasmas became the breakthrough that allowed the features in integrated circuits to continue to shrink over the next 40 years. Some of this early history is reviewed, and a discussion of the evolution in plasma reactor design is included. Some basic principles related to plasma etching such as evaporation rates and Langmuir–Hinshelwood adsorption are introduced. Etching mechanisms of selected materials, silicon, silicon dioxide, and low dielectric-constant materials are discussed in detail. A detailed treatment is presented of applications in current silicon integrated circuit fabrication. Finally, some predictions are offered for future needs and advances in plasma etching for silicon and nonsilicon-based devices.

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Plasma etching: Yesterday, today, and tomorrow

A lithographic projection apparatus includes a liquid confinement structure extending along at least a part of a boundary of a space between a projection system and a substrate table. The liquid confinement structure is positioned adjacent a final surface of the projection system and includes a first inlet configured to supply a liquid, through which a patterned beam is to be projected, to the space, and a second inlet configured to supply gas and formed in a face of the structure. The face is arranged to oppose a surface of the substrate and the second inlet is located radially outward, with respect to an optical axis of the projection system, of the space and has a porous member to evenly distribute gas flow over an area of the second inlet.

Lithographic Projection Apparatus

Commercial EUV lithographic systems require multilayers with higher reflectance and better stability than those published to date This work represents our effort to meet these specifications Interface-engineered Mo-Si multilayers with 70% reflectance and 0545-nm bandwidth at 135-nm wavelength and 71% reflectance with 049-nm bandwidth at 127-nm wavelength were developed These results were achieved with 50 bilayers These new multilayers consist of alternating Mo and Si layers separated by thin boron carbide layers Depositing boron carbide on the interfaces leads to reduction in molybdenum silicide formation of the Mo-on-Si interfaces Bilayer contraction is reduced by 30%, implying that there is less intermixing of Mo and Si to form silicide As a result, the Mo-on-Si interfaces are sharper in interface-engineered multilayers than in standard Mo-Si multilayers The optimum boron carbide thicknesses have been determined and appear to be different for the Mo-on-Si and Si-on-Mo interfaces The best results were obtained with 04-nm-thick boron carbide layers for the Mo-on-Si interfaces and 025-nm-thick boron carbide layers for the Si-on-Mo interfaces The increase in reflectance is consistent with multilayers having sharper and smoother interfaces A significant improvement in oxidation resistance of EUV multilayers has been achieved with ruthenium-terminated Mo-Si multilayers The best capping-layer design consists of a Ru layer separated from the top Si layer by a boron carbide diffusion barrier This design achieves high reflectance and the best oxidation resistance during EUV exposure in a water-vapor (oxidizing) environment Electron-beam exposures of 45 h (in an effort to simulate EUV exposure perturbation of the top layers) in the presence of 5×10 - 7 -Torr water-vapor partial pressure show no measurable reflectance loss and no increase in the oxide thickness of Ru-terminated multilayers

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Improved reflectance and stability of Mo-Si multilayers

ldquoTrenchrdquo capacitors containing multiple metal-insulator-metal (MIM) layer stacks are realized by atomic-layer deposition (ALD), yielding an ultrahigh capacitance density of 440 at a breakdown voltage VDB > 6 V. This capacitance density on silicon is at least 10times higher than the values reported by other research groups. On a silicon substrate containing high-aspect-ratio macropore arrays, alternating MIM layer stacks comprising high-k Al2O3dielectrics and TiN electrodes are deposited using optimized ALD processing such that the conductivity of the TiN layers is not attacked. Ozone annealing subsequent to each Al2O3 deposition step yields significant improvement of the dielectric isolation and breakdown properties.

Ultrahigh Capacitance Density for Multiple ALD-Grown MIM Capacitor Stacks in 3-D Silicon

In-situ cleaning of optical components for use in a lithographic projection apparatus can be carried out by irradiating a space within the apparatus containing the optical component with UV or EUV radiation having a wavelength of less than 250 nm, in the presence of molecular oxygen. Generally, the space will be purged with an ozoneless purge gas which contains a small amount of molecular oxygen in addition to the usual purge gas composition. The technique can also be used in an evacuated space by introducing a low pressure of molecular oxygen into the space.

Lithographic projection apparatus, device manufacturing method and device manufactured thereby

This paper reviews the options of using Atomic Layer Deposition (ALD) in passive and heterogeneous integration. The miniaturization intended by both integration schemes aim at Si-based integration for the former and at die stacking in a compact System-in-Package for the latter. In future Si-based integrated passives a next miniaturization step in trench capacitors requires the use of multiple ‘classical’ MOS layer stacks and the use of so-called high-k dielectrics (based on HfO2, etc.) and novel conductive layers like TiN, etc. to compose MIS and MIM stacks in ‘trench’ and ‘pore’ capacitors with capacitance densities exceeding 200 nF/mm 2 . One of the major challenges in realizing ultrahigh-density trench capacitors is to find an attractive pore lining and filling fabrication technology at reasonable cost and reaction rate as well as low temperature (for back-end processing freedom). As the deposition for the dielectric and conductive layers should be highly uniform, step-conformal and lowtemperature (≤ 400 °C), ALD is an enabling technology here, by virtue of the self-limiting mechanism of this layer-by-layer deposition technique. This article discusses first a few examples of LPCVD deposition of conventional MOS layers with ONO-dielectrics and in situ doped polycrystalline silicon, both as single layers and multilayer stacks. In addition, a few options for ALD deposition of thin dielectric and conductive layers (e.g. HfO2- and TiN-based) will be discussed. The silicon substrates that were used contained high aspect ratio (≥ 20) features with cross-section and spacing of the order of 1 µm.

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ALD Options for Si-integrated Ultrahigh-density Decoupling Capacitors in Pore and Trench Designs

An EUV radiation source unit (10) for use in a lithographic projection apparatus to illuminate a mask pattern (22) which is to be projected on a substrate (W) comprises an electron source (12) and a medium in which the electrons of the source generate EUV Cherenkov radiation (PB). The wavelengths of the Cherenkov radiation and the multilayer structure of the mirrors (31-34) of the projection system (30) are adapted to each other, so that these mirrors show a maximum reflectivity. The medium forms part of the mask (MA) so that a mirror condenser system is no longer needed. In this way, an efficient transmission of radiation (PB) from the source to the substrate is obtained.

Method of imaging a mask pattern on a substrate by means of EUV radiation, and apparatus and mask for performing the method

This paper describes the deposition of high-k dielectric layers, Al2O3, Ta2O5, HfO2, etc, in high aspect ratio pores aiming for a higher capacitance density at a given breakdown voltage. The most emerging technology to achieve this appears to be Atomic Layer Deposition, ALD. However, applying ALD to wafers with deep pores leads to additional challenges to be dealt with. Apart from e.g. roughness on the sidewalls of the pores, leading to undesired lower breakdown voltages, and native oxide layers, leading to undesired lower relative dielectric constants, carrying out ALD on wafers with a large topography needs careful consideration of the ALD process. An appropriate step coverage and proper microstructure (morphology and texture) are necessary to achieve good insulating layers, but are certainly not obvious! This paper addresses issues we ran into in our challenge to realize very high capacity densities (preferably > 200 nF/mm) with sufficient insulating quality.

Extremely high-density capacitors with ald high-k dielectric layers

A method of manufacturing multilayer mirrors for use in conjunction with X-rays. Customary multilayer mirrors are composed of discrete, thin layers which generally consist of alternating absorption and spacer layers. In order to counteract surface roughness of the thin layers, it is known to smoothen the layers by ion etching after deposition. A drawback thereof consists in that the material of one layer penetrates into the other layer, so that the location of the interface and the thickness of the layers of the multilayer mirror are no longer suitably defined. In accordance with the invention, a multilayer mirror is manufactured by stimulating the penetration of one of the materials into the layer with the other material, after which the original layer thickness of the first material is removed by etching. By repeating this process one layer after the other, a multilayer mirror is obtained which does not consist of an alternation of uniform, discrete layers of a different material but of recurrent layers of one of the materials in which the other material has penetrated.

Multilayer mirror with a variable refractive index

The very large development of home and domestic electronic appliances as well as portable device has led the microelectronics industry to evolve in two complimentary directions : “ More Moore ” with the continuous race towards extremely small dimensions hence the development of SoCs (System on Chip) and more recently a new direction that we could name “ More than Moore ” with the integration of devices that were laying outside the chips and here the creation of SiPs (System in Package). These two approaches are not in competition one with the other: the paper will show some examples of integrated nano systems that use several SoCs. The technology we have developed is called Silicon Based System in Package. The first products using this technology are now in volume production and used mainly in the field of wireless communications. This new technology relies on four pillars. Passive integration is the first. Very efficient and high quality factor capacitors and inductors have been integrated, allowing the creation of complete modules including active devices, filters and decoupling capacitors. High-density MOS capacitors with 1-1000 nF capacitance, and as high values as 25-250+ nF/mm 2 specific capacitance have been fabricated in macroporous Si-wafers, containing over 1 billion macropores. Typically an ESR less than 100 mU and an ESL less than 25 pH were found for capacitors over 10 nF. This novel concept is an important step forward in improving the stability of power-amplifier modules by replacing conventional SMD technology. Whereas generations with capacitors density of up to 100 nF/mm 2 will be using “conventional” materials and structures, the next steps in the roadmap will call for new 3D structures and materials such as high-k dielectric. The second element is advanced packaging. New technologies, such as the assembly of Silicon chips onto other Silicon chips, also named “double flip chip” have been developed. This has been made possible thanks to the combination of the most advanced microbumping and die placement techniques. In addition to a tremendous reduction of size (up to a factor of 10 to 20) these techniques have also brought a better repeatability of system performance. The third element has been the development of design tools that allow a seamless system design for engineers used to IC design tools and flows. Our Design Environment allows co design of multiple technologies chips and their integration in a single system. This IC-like Design Environment has contributed a lot to the adoption of the technology. Testing is the fourth element and is one of the economical enablers of the technology. The key words are: “known good die”, RF test, system test, etc. Some innovative RF probing and full on wafer subsystem test will be shown. Even though efficient test is not vital for the technical feasibility of this system integration, it becomes very quickly one of the most important enablers, especially when we deal with very high volumes of production. The conclusion of the paper will be an open door to the future. Some innovations like the integration of light or even energy storage inside our SiPs will be presented.

Silicon Based System-in-Package : Breakthroughs in Miniaturization and ‘Nano’-integration Supported by Very High Quality Passives and System Level Design Tools

Jan Verhoeven

Papers

ALD Options for Si-integrated Ultrahigh-density Decoupling Capacitors in Pore and Trench Designs

Method of imaging a mask pattern on a substrate by means of EUV radiation, and apparatus and mask for performing the method

Extremely high-density capacitors with ald high-k dielectric layers

Multilayer mirror with a variable refractive index

Silicon Based System-in-Package : Breakthroughs in Miniaturization and ‘Nano’-integration Supported by Very High Quality Passives and System Level Design Tools