Solid-state switch-mode rectification converters have reached a matured level for improving power quality in terms of power-factor correction (PFC), reduced total harmonic distortion at input AC mains and precisely regulated DC output in buck, boost, buck-boost and multilevel modes with unidirectional and bidirectional power flow. This paper deals with a comprehensive review of improved power quality converters (IPQCs) configurations, control approaches, design features, selection of components, other related considerations, and their suitability and selection for specific applications. It is targeted to provide a wide spectrum on the status of IPQC technology to researchers, designers and application engineers working on switched-mode AC-DC converters. A classified list of more than 450 research publications on the state of art of IPQC is also given for a quick reference.

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A review of single-phase improved power quality AC-DC converters

The authors discuss high-voltage power conversion. Conventional series connection and three-level voltage source inverter techniques are reviewed and compared. A novel versatile multilevel commutation cell is introduced: it is shown that this topology is safer and more simple to control, and delivers purer output waveforms. The authors show how this technique can be applied to either choppers or voltage-source inverters and generalized to any number of switches.<<ETX>>

Multi-level conversion : high voltage choppers and voltage-source inverters

Introduction to Electromagnetic Compatibility

In the first part of this paper, three-phase power factor correction (PFC) rectifier topologies with sinusoidal input currents and controlled output voltage are derived from known single-phase PFC rectifier systems and/or passive three-phase diode rectifiers. The systems are classified into hybrid and fully active pulsewidth modulation boost-type or buck-type rectifiers, and their functionality and basic control concepts are briefly described. This facilitates the understanding of the operating principle of three-phase PFC rectifiers starting from single-phase systems, and organizes and completes the knowledge base with a new hybrid three-phase buck-type PFC rectifier topology denominated as Swiss Rectifier. Finally, core topics of future research on three-phase PFC rectifier systems are discussed, such as the analysis of novel hybrid buck-type PFC rectifier topologies, the direct input current control of buck-type systems, and the multi-objective optimization of PFC rectifier systems. The second part of this paper is dedicated to a comparative evaluation of four rectifier systems offering a high potential for industrial applications based on simple and demonstrative performance metrics concerning the semiconductor stresses, the loading and volume of the main passive components, the differential mode and common mode electromagnetic interference noise level, and ultimately the achievable converter efficiency and power density. The results are substantiated with selected examples of hardware prototypes that are optimized for efficiency and/or power density.

The Essence of Three-Phase PFC Rectifier Systems—Part II

An advantage for some wide bandgap materials, that is often overlooked, is that the thermal coefficient of expansion (CTE) is better matched to the ceramics in use for packaging technology. It is shown that the optimal choice for uni-polar devices is clearly GaN. It is further shown that the future optimal choice for bipolar devices is C (diamond) owing to the large bandgap, high thermal conductivity, and large electron and hole mobilities. A new expression relating the critical electric field for breakdown in abrupt junctions to the material bandgap energy is derived and is further used to derive new expressions for specific on-resistance in power semiconductor devices. These new expressions are compared to the previous literature and the efficacy of specific power devices, such as heterojunction MOSFETs, using GaN are discussed.

An assessment of wide bandgap semiconductors for power devices

The paper presents a physical structure optimizat ion of an integrated semiconductor device design: a power MOSFET and other vertical transistors are integrated within the same die, introducing a novel self supplied power transistor This integrat ed optimal design leads to complex optimization problems with close constraints The main constrain t deals with the avalanche phenomenon that is formulated by multiple integral expressions of nume rical functions The paper focuses on two aspects: the integral formulation of the avalanche model and mor e specifically its gradient computation in the view of applying a gradient-based optimization algorithm, a nd the comparisons of several optimization methods on this problem Keywords : Genetic optimization algorithms, gradient-based o ptimization algorithm, integration constraint, Power MOSFETs, design of monolithically integrated circuits

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Optimization of a power mosfet and its monolithically integrated self-powering circuits

Due to the increase of the switching speed of power devices, the impact of the gate driver parasitic capacitances has a influence on the dynamic behaviour in the switching cell. Here, the study is focused on the dynamic behaviour for series-connected SiC-MOSFET devices: a predictive model that considers the parasitic capacitances is developed and compared to simulation results. Then, experimental results validate the proposed modelling.

A predictive model to investigate the effects of gate driver on dv/dt in series-connected SiC-MOSFETs

Diamond is not only known for being the hardest gemstone but also for being the semiconductor having the highest calculated figures of merit (FOM). This comes from the unique physical properties of this material. Thus, it is predicted that diamond should exceeds silicon carbide (SiC) and galium nitride (GaN) in terms of low loss device and better compromises for on-state resistance versus breakdown voltage. However, in practice the applications of diamond devices are still limited and the performances are still not reaching the theoretical predictions. The question is then how to predict and evaluate diamond device performances themselves and in their environment. One of the possible answer is by using finite element based softwares. Few reports exist on unipolar diamond device modeling, and none on diamond bipolar device. The main limitations come from the lack of parameters implemented in the simulation tools together with the difficulties for modeling wide band gap semiconductor, i.e. extremely low carrier concentrations. In this study, we present the results on the first simulation of a diamond bipolar junction transistor electrical characteristics. The validation of the simulation is the first step towards the prediction of the architecture and behavior of future diamond devices.

Diamond bipolar device simulation

The paper deals with arrays of numerous power conversion cells, associated in series and/or in parallel to build larger step up or step down direct current (DC)/DC isolated converters. The work focuses on the impact of the spread and distribution of the conversion cell characteristics on the characteristics and performance of the power converter array (PCA). Based on a characterization protocol, about 130 conversion standard cells (CSC) are characterized and classified from a statistical point of view. Three families are defined and representatives are chosen and implemented in various configurations, in open and closed loop control, to analyze the impact of their spread characteristic over the global converter, the PCA. The paper is based on an extended practical set up and protocols, all described in details. Guidelines on CSCs implementation with respect to their dispersion are provided at the end on the paper.

https://www.mdpi.com/2079-9292/8/9/917/pdf

Impact of Component Dispersion in DC to DC Low-Power Low-Voltage Power Converter Array

This article presents the analysis and management of differential mode conducted EMI in modular converters made from associations of standard conversion cells. Two main configurations, inputs in series—outputs in parallel and inputs in parallel—outputs in series are studied with the objective to define a generic EMI management technique, independent from the number of conversion standard cells implemented. First, analysis is carried out from a theoretical point of view based on simplified models. Second, filtering solutions are introduced and compared. Especially, centralized versus distributed filtering techniques are compared with the objective to find generic solutions. The results are compared and validated with practical characterizations.

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Jean-Christophe Crebier

Papers

Optimization of a power mosfet and its monolithically integrated self-powering circuits

A predictive model to investigate the effects of gate driver on dv/dt in series-connected SiC-MOSFETs

Diamond bipolar device simulation

Impact of Component Dispersion in DC to DC Low-Power Low-Voltage Power Converter Array

Handling Differential Mode Conducted EMC in Modular Converters