Solid-state switch-mode rectification converters have reached a matured level for improving power quality in terms of power-factor correction (PFC), reduced total harmonic distortion at input AC mains and precisely regulated DC output in buck, boost, buck-boost and multilevel modes with unidirectional and bidirectional power flow. This paper deals with a comprehensive review of improved power quality converters (IPQCs) configurations, control approaches, design features, selection of components, other related considerations, and their suitability and selection for specific applications. It is targeted to provide a wide spectrum on the status of IPQC technology to researchers, designers and application engineers working on switched-mode AC-DC converters. A classified list of more than 450 research publications on the state of art of IPQC is also given for a quick reference.

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A review of single-phase improved power quality AC-DC converters

The authors discuss high-voltage power conversion. Conventional series connection and three-level voltage source inverter techniques are reviewed and compared. A novel versatile multilevel commutation cell is introduced: it is shown that this topology is safer and more simple to control, and delivers purer output waveforms. The authors show how this technique can be applied to either choppers or voltage-source inverters and generalized to any number of switches.<<ETX>>

Multi-level conversion : high voltage choppers and voltage-source inverters

Introduction to Electromagnetic Compatibility

In the first part of this paper, three-phase power factor correction (PFC) rectifier topologies with sinusoidal input currents and controlled output voltage are derived from known single-phase PFC rectifier systems and/or passive three-phase diode rectifiers. The systems are classified into hybrid and fully active pulsewidth modulation boost-type or buck-type rectifiers, and their functionality and basic control concepts are briefly described. This facilitates the understanding of the operating principle of three-phase PFC rectifiers starting from single-phase systems, and organizes and completes the knowledge base with a new hybrid three-phase buck-type PFC rectifier topology denominated as Swiss Rectifier. Finally, core topics of future research on three-phase PFC rectifier systems are discussed, such as the analysis of novel hybrid buck-type PFC rectifier topologies, the direct input current control of buck-type systems, and the multi-objective optimization of PFC rectifier systems. The second part of this paper is dedicated to a comparative evaluation of four rectifier systems offering a high potential for industrial applications based on simple and demonstrative performance metrics concerning the semiconductor stresses, the loading and volume of the main passive components, the differential mode and common mode electromagnetic interference noise level, and ultimately the achievable converter efficiency and power density. The results are substantiated with selected examples of hardware prototypes that are optimized for efficiency and/or power density.

The Essence of Three-Phase PFC Rectifier Systems—Part II

An advantage for some wide bandgap materials, that is often overlooked, is that the thermal coefficient of expansion (CTE) is better matched to the ceramics in use for packaging technology. It is shown that the optimal choice for uni-polar devices is clearly GaN. It is further shown that the future optimal choice for bipolar devices is C (diamond) owing to the large bandgap, high thermal conductivity, and large electron and hole mobilities. A new expression relating the critical electric field for breakdown in abrupt junctions to the material bandgap energy is derived and is further used to derive new expressions for specific on-resistance in power semiconductor devices. These new expressions are compared to the previous literature and the efficacy of specific power devices, such as heterojunction MOSFETs, using GaN are discussed.

An assessment of wide bandgap semiconductors for power devices

This paper presents an adaptive gate drive circuit to provide a safer and more efficient control of Wide Bandgap Devices (WBD). The gate drive circuit fabricated in AMS0.35μm HV CMOS technology has an adaptive output impedance for optimal turn-on/off driving conditions and a gate side power transistor switching transition detection. Its impedance can be precisely adjusted from 0.7Ω to 12.5Ω during transition time accordingly to the switched current to reduce overvoltage due to parasitic inductances. It can also be set to maintain the same transition times of WBD over operating point and temperature variations. Therefore, in an 800 kHz switching frequency synchronous buck converter based on WBD, the proposed gate drive circuit demonstrates secure but drastic dead-time reduction with a peak performance gain of 20% compared to a fixed dead-time of 50ns.

https://hal.archives-ouvertes.fr/hal-00988293/document

An adaptive output impedance gate drive for safer and more efficient control of Wide Bandgap Devices

Nowadays, MOSFET and IGBT components are widely used in medium and high power converters. They are subjected to increasing requirements: electrical performances, simple implementation, reliability, integration, smaller volume and price. Moreover, their integration process offers the possibility to reduce and to eliminate the need for pick and place, bonding (wafer-and/or ball-bonding) and other assembly processes necessary in hybrid assemblies, and in the same time to add some useful functionality like sensors for protection and control. This paper presents a possible solution for the monolithic integration of over voltage protection circuits for power MOSFETs or IGBTs. The solution contains a vertical JFET transistor, integrated together, in the same die, with the main switch (MOSFET/IGBT). The specific characteristic of vertical JFET with diffused gates is used to control over voltage and voltage balance among devices associated in series connection. Thanks to voltage threshold control, the voltage protection level can be adjusted under operation. This new feature allows modifying the protection level and smoothness thanks to operating conditions. It allows redistributing voltage balance when one of several units, in the series connection, is out of operation, allowing the operation under failure mode operation. In addition, switching smoothness can also be adjusted thanks to VJFET control sensitivity. The paper presents the power electronic application fields. Then, vertical JFET operation and characteristics will be recalled. It is shown how it can be used for over voltage management. Two solutions are presented. One of them is studied and experimented to highlight the operation principles. Experimental results are provided based on prototypes realized, including a power MOSFET and a V-JFET within the same voltage terminations. Monolithic integration conditions are briefly addressed

V-JFET Transistors for over voltage protection in power device series connected applications

This paper deals with the design, the realization and the characterization of an integrated converter for low voltage and low power, isolated applications (3.3 V, 1 W). It is based on the association of two generic silicon dies performing DC to AC and AC to DC operations. The power dies are designed in CMOS technology and operate at high frequency (1 MHz) and high efficiency. This high power density realization includes the power circuit and the control electronic. The integrated conversion structure can operate as an inverter or as a rectifier in a wide range of power flows and input voltages. Three important issues are addressed in this paper: design of the power part at high efficiency, reduced consumption of the control electronic and the gate drivers, and implementation with reduced parasitic behavior. The practical implementation and characterization are also addressed in a second part. First tests are carried out with packaged dies on PCB boards, in order to simplify the implementation. The efficiency of the inverter reaches up to 92% as a function of input voltage with these conditions. The second experimental investigation is a full DC to DC converter implemented with two CMOS power dies (one inverter and one rectifier) together with an HF transformer and an output LC filter. This article ends with the study of the packaging in order to minimize parasitics elements, such as resistances and inductances, which can be very harmful for the global efficiency of our micro-converter.

https://hal.archives-ouvertes.fr/docs/00/42/25/18/PDF/0532-epe2009-full-17150325.pdf

Design and realization of autonomous power CMOS single phase inverter and rectifier for low power conditioning applications

In power converter configurations like multi-cell, multi-level, series connection of power devices etc. under very high switching speeds, several dv/dt sources generated at different floating points produce conducted EMI perturbations from the power part to the control part through the many gate driver circuitries. The modifications of the parasitic capacitive propagation paths between the power and the control sides have impacts on the circulating current produced by high dv/dt, which, in turns, affects the voltages distributions (static and transient) among the power devices. This paper presents news architectures for gate drivers power supplies implementations in series connection to minimize parasitic currents, especially reducing the common mode currents and to minimize the unbalance voltages of SiC-MOSFET devices in series connections. Simulations and experiments validate the advantages of the gate driver power supplies proposed architectures on the common mode currents and drain-to-source voltages of series-connected devices.

Gate Driver Architectures Impacts on Voltage Balancing of SiC MOSFETs in Series Connection

This study deals with the power electronics packaging and the needs for additional knowledge about electrical pressed contact behavior. For this, a measure bench has been realized. It is able to characterize the pressed interface between a metal electrode and a power chip as a function of the clamping force (0-8000N) and the temperature (up to 100°C). First measurement results show that the electrical contact resistance is negligible compared to the chip on-state voltage. Second measurement results show that the high value of the chip metallization resistance masks also the contact resistance. Finally, it appears that it is necessary to estimate the chip contact zone influences on the current repartition. Then a method based on both, the use of a chip model and the measurements directly on the chip, has been developed. It is able to look for the steady state current repartition in the chip as a function of the contact zone and the chip metallization physical parameters.

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Jean-Christophe Crebier

Papers

An adaptive output impedance gate drive for safer and more efficient control of Wide Bandgap Devices

V-JFET Transistors for over voltage protection in power device series connected applications

Design and realization of autonomous power CMOS single phase inverter and rectifier for low power conditioning applications

Gate Driver Architectures Impacts on Voltage Balancing of SiC MOSFETs in Series Connection

Electrical characterization of a pressed contact between a power chip and a metal electrode