Jelena Notaros

TL;DR: A way of integrating photonics with silicon nanoelectronics is described, using polycrystalline silicon on glass islands alongside transistors on bulk silicon complementary metal–oxide–semiconductor chips to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing.

TL;DR: This article introduces a single-chip OPA realized through wafer-scale 3-D integration of silicon photonics and CMOS, and achieves wide-range 2-D steering over 18.25° beamwidth while consuming 20 mW/element average power.

TL;DR: Apodized bi-level fiber-to-chip grating couplers, designed using a complex-wavevector band-structure approach, are demonstrated in a commercially available, monolithic SOI CMOS process achieving 92% (-0.36dB) coupling efficiency.

TL;DR: This article demonstrates the first monolithically integrated erbium-doped tunable laser on a complementary-metal-oxide-semiconductor (CMOS)-compatible silicon photonics platform and achieves a tunability from 1527 nm to 1573 nm, with a >40 dB side mode suppression ratio (SMSR).

TL;DR: In this article, an advanced CMOS-compatible 300mm-wafer silicon-photonics platform is introduced that consists of a silicon layer with eight doping masks, two silicon-nitride layers, three metal and via layers, a dicing trench for smooth edge-coupled facets, and a gain-film trench that enables interaction between the gain material and waveguide layers.