An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

An object of the present invention is to decrease the resistance of a power supply line, to suppress a voltage drop in the power supply line, and to prevent defective display. A connection terminal portion includes a plurality of connection terminals. The plurality of connection terminals is provided with a plurality of connection pads which is part of the connection terminal. The plurality of connection pads includes a first connection pad and a second connection pad having a line width different from that of the first connection pad. Pitches between the plurality of connection pads are equal to each other.

Semiconductor device and display device

A gate-insulated thin film transistor is disclosed. One improvement is that the thin film transistor is formed on a substrate through a blocking layer in between so that it is possible to prevent the transistor from being contaminated with impurities such as alkali ions which exist in the substrate. Also, a halogen is added to either or both of the blocking layer and a gate insulator of the transistor in order that impurities such as alkaline ions, dangling bonds and the like can be neutralized, therefore, the reliability of the device is improved.

Thin-film transistor

To provide a semiconductor display device capable of displaying an image having clarity and a desired color, even when the speed of deterioration of an EL layer is influenced by its environment. Display pixels and sensor pixels of an EL display each have an EL element, and the sensor pixels each have a diode. The luminance of the EL elements of each in the display pixels is controlled in accordance with the amount of electric current flowing in each of the diodes.

Semiconductor display device

Disclosed is a display device including a transistor showing extremely low off current. In order to reduce the off current, a semiconductor material whose band gap is greater than that of a silicon semiconductor is used for forming a transistor, and the concentration of an impurity which serves as a carrier donor of the semiconductor material is reduced. Specifically, an oxide semiconductor whose band gap is greater than or equal to 2 eV, preferably greater than or equal to 2.5 eV, more preferably greater than or equal to 3 eV is used for a semiconductor layer of a transistor, and the concentration of an impurity which serves as a carrier donor included is reduced. Consequently, the off current of the transistor per micrometer in channel width can be reduced to lower than 10 zA/μm at room temperature and lower than 100 zA/μm at 85° C.

Display device and manufacturing method thereof

Results on indium-oxide-based transparent oxide TFTs, which the active layer is prepared by DC sputtering, are presented. The fabricated TOS TFTs show high mobility (37 cm2/V-s), high ON/OFF current ratio and large on-state current. Fabricating oxide TFTs on temperature-sensitive substrates is also attainable owing to the low temperature process of the active layer preparation.

15.4: Excellent Performance of Indium‐Oxide‐Based Thin‐Film Transistors by DC Sputtering

The dynamic stress switching of p-channel polycrystalline-silicon (poly-Si) thin-film transistors from full depletion to accumulation bias creates the high electric field near source/drain (S/D) junctions due to the slow formation of the accumulated electrons at the SiO2/poly -Si interface. The high electric field causes impact ionization near the S/D, where the secondary electrons surmount the SiO2 barrier and are trapped near the interface. The channel region near the S/D is inverted to p-type by the trapped electrons, and the effective channel length is reduced. The drain current increases with the stress time, particularly for short-channel devices.

Dynamic Bias Instability of p-Channel Polycrystalline-Silicon Thin-Film Transistors Induced by Impact Ionization

This letter studies the nonvolatile memory characteristics of polycrystalline-silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon (SONOS) structure. As the device was programmed, significant trap-assisted gate-induced drain leakage current was observed due to the extra programmed electrons trapped in the nitride layer which lies above the gate-to-drain overlap region. In order to suppress the leakage current and thereby avoid signal misidentification, we utilized band-to-band hot hole injection into the nitride layer. Because the injected hot holes can remain in the nitride layer after repeated Fowler-Nordheim erase and program operations, this method can exhibit good sustainability in such a SONOS-TFT memory device.

Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device

Improvement of the SiO/sub 2//Si interface degradation due to hot-electron injections from silicon by repeated irradiation-then-anneal treatments is described. Each treatment includes an irradiation of Co-60 with a total dose of 10/sup 6/ rd (SiO/sub 2/) and an anneal in N/sub 2/ for 10 min successively. It is found that the sensitivity to hot-electron induced damage decreases gradually as the number of irradiation-then-anneal treatments increases. After three such treatments, the MOS capacitor shows excellent behavior in terms of its hardness to hot-electron-induced degradation. >

Improvement of hot-electron-induced degradation in MOS capacitors by repeated irradiation-then-anneal treatments

This letter investigates the degradation mechanism of polycrystalline silicon thin-film transistors with a silicon-oxide-nitride-oxide-silicon structure under off -state stress. During the electrical stress, the hot hole generated from band-to-band tunneling process will inject into gate dielectric, and the significant on-state degradation (more than 1 order) indicates that the interface states are accompanied with hot-hole injection. In addition, the asymmetric I- V characteristics indicate that the interface states are located near the drain side. Moreover, the ISE-TCAD simulation tool was utilized to model the degradation mechanism and analyze trap states distribution. Although both the vertical and lateral electrical fields are factors for degradation and hot-hole injection, the degradation is mainly affected by the lateral electrical field over a critical point.

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Jim-Shone Chen

Papers

15.4: Excellent Performance of Indium‐Oxide‐Based Thin‐Film Transistors by DC Sputtering

Dynamic Bias Instability of p-Channel Polycrystalline-Silicon Thin-Film Transistors Induced by Impact Ionization

Improvement of Memory State Misidentification Caused by Trap-Assisted GIDL Current in a SONOS-TFT Memory Device

Improvement of hot-electron-induced degradation in MOS capacitors by repeated irradiation-then-anneal treatments

Analysis of Degradation Mechanism in SONOS-TFT Under Hot-Carrier Operation