Showing papers by "João Goes published in 2010"

Two-stage fully-differential inverter-based self-biased CMOS amplifier with high efficiency

Abstract: This paper describes a novel two-stage fully-differential CMOS amplifier comprising two self-biased inverter stages, with optimum compensation and high efficiency. Although it relies on a class A topology, it is shown through simulations, that it achieves the highest efficiency of its class and comparable to the best class AB amplifiers. Due to the self-biasing, a low variability in the DC gain over process, temperature, and supply is achieved. A detailed circuit analysis, a design methodology for optimization and the most relevant simulation results are presented, together with a final comparison among state-of-the-art amplifiers.

MOSFET-only wideband LNA with noise cancelling and gain optimization

Abstract: In this paper we present a MOSFET-only implementation of a balun LNA. This LNA is based on the combination of a common-gate and a common-source stage with cancelling of the noise of the common-gate stage. In this circuit, we replace resistors by transistors, to reduce area and cost, and minimize the effect of process and supply variations and mismatches. In addition we obtain a higher gain for the same voltage drop. Thus, the LNA gain is optimized and the noise figure (NF) is reduced. We derive equations for the gain, input matching and NF. We compare the performance of this new topology with that of a conventional LNA with resistors. Simulation results with a 130 nm CMOS technology show that we obtain a balun LNA with a peak 19.8 dB gain (about 2 dB improvement), a spot NF lower than 1.9 dB (0.5 dB reduction). The total power consumption is only 4.8 mW for a wide bandwidth higher than 6 GHz.

An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification

Abstract: This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features an active area below 0.12 mm2, where only MOS devices are used. Measurement results for a 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3 dB of spurious-free dynamic range, -47.5 dB of total harmonic distortion, 39.1 dB of signal-to-noise-plus-distortion ratio, and 6.2 bits of peak effective number of bits while consuming less than 14 mW from a 1.2-V supply.

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

Abstract: This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.

A small-area self-biased wideband CMOS balun LNA with noise cancelling and gain enhancement

Abstract: In this paper we present a low-power and small-area balun LNA. The proposed inverter-based topology uses self-biasing and noise cancelling, yielding a very robust LNA with a low NF. Comparing this circuit with a conventional inverter-based circuit, we obtain a ∼3 dB enhancement in voltage gain, with improved robustness against PVT variations. Simulations results in a 130 nm CMOS technology show a 17.7dB voltage gain, nearly flat over a wide bandwidth (200MHz–1GHz), and an NF of approximately 4dB. The total power consumption is below 7.5 mW, with a very small die area of 0.007 mm2. All data are extracted from post-layout simulations.

Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs

Abstract: In this paper we present a reconfigurable architecture for coherent built-in self-testing (BIST) of high speed IQ ADCs with moderate resolutions. The proposed system can be fully integrated with the ADC and, besides a low-jitter clock reference, no other external high quality generators are required. A locked system comprising a first phase-locked loop (PLL) with two IQ linear outputs and a second PLL with a squared output signal are proposed as well as the dedicated voltage-controlled oscillator (VCO) circuits. To illustrate the simplicity of the proposed solution, the system is designed, parameterized and simulated targeting the BIST of a 6-bit 1 GS/s ADC.

Low-Power Open Loop Multiply-by-two Amplifier with Gain-accuracy Improved by Local-Feedback

Abstract: This paper proposes the complete electrical design of a new multiply-by-two amplifier to be readily used in ultra high-speed medium resolution pipeline ADC stages. It is based in a switched-capacitor open-loop structure but with the novelty of having the gain accuracy improved by using an active amplifier with local feedback. Simulation results demonstrate that, with a very low-power dissipation and without employing any digital self-calibration or gain-control techniques, the circuit exhibits, over PVT corner and device mismatches, a dynamic performance and a gain-accuracy compatible with 6-bit level.

Analysis and design of a MOSFET-only wideband balun LNA

Abstract: In this paper we present a MOSFET-only implementation of a balun LNA. This LNA is based on the combination of a common-gate and a common-source stage with cancellation of the noise of the common-gate stage. In this circuit, we replace resistors by transistors, to reduce area and cost, and to minimize the effect of process and supply variations and mismatches. In addition, we obtain a higher gain for the same voltage drop. Thus, the LNA gain is optimized and the noise figure (NF) is reduced. We derive equations for the gain, input matching and NF. The performance of this new topology is compared with that of a conventional LNA with resistors. Simulation results with a 130 nm CMOS technology show that we obtain a balun LNA with a peak gain of 20.2 dB (about 2 dB improvement), and a spot NF lower than 2.4 dB. The total power consumption is only 4.8 mW for a bandwidth higher than 6 GHz

MOSFET-only Mixer/IIR filter with gain using parametric amplification

Abstract: This paper describes the design of a discrete-time passive Mixer/IIR filter. The use of an improved MOS Parametric Amplification leads to a moderate gain in the signal path and improved noise performance, instead of the conversion loss inherent to passive mixers. Simulation results demonstrate that, employing the proposed MPA structure based on a modified double-complementary topology with floating terminals, an improvement of over 4 dB in the overall circuit gain and up to 2 dB in the noise figure can be achieved.

A CMOS Inverter-Based Self-biased Fully Differential Amplifier

Abstract: A CMOS self-biased fully differential amplifier is presented. Due to the self-biasing structure of the amplifier and its associated negative feedback, the amplifier is compensated to achieve low sensitivity to process, supply voltage and temperature (PVT) variations. The output common-mode voltage of the amplifier is adjusted through the same biasing voltages provided by the common-mode feedback (CMFB) circuit. The amplifier core is based on a simple structure that uses two CMOS inverters to amplify the input differential signal. Despite its simple structure, the proposed amplifier is attractive to a wide range of applications, specially those requiring low power and small silicon area. As two examples, a sample-and-hold circuit and a second order multi-bit sigma-delta modulator either employing the proposed amplifier are presented. Besides these application examples, a set of amplifier performance parameters is given.

Purely-digital versus mixed-signal self-calibration techniques in high-resolution pipeline ADCs

Abstract: This paper describes and compares some of the most energy and area efficient self-calibration techniques reported over the past years. Additional techniques used to further improve power dissipation are briefly described as well. A robust mixed-signal self-calibration technique is proposed, in which, the multi-bit first stage in the ADC is calibrated without requiring any modifications, as long as the ideal conversion characteristic of this stage is known. A novel Gaussian Noise Generator is used as the input analog stimulus and, on the digital side, the calibration algorithm does not require explicit multiplications, which greatly simplifies the digital circuitry. Experimental measurements of a 13-bit ADC fabricated in 90 nm CMOS, after calibration and at 40 MS/s, show that the SFDR is improved by over 14 dB (to 84 dB), the THD is improved by over 10 dB (to −80 dB), achieving a peak ENOB of 11.3 bits for a 10 MHz input and with a 1.2 V power supply.

Digitally programmable delay-locked-loop with variable charge pump current

Abstract: This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. The architecture of the programmable delay uses a ΣΔ modulator to generate a reference clock with a delay unaffected by component matching. This reference clock has a large jitter noise component that is filtered by delay lock loop (DLL). The programmable delay can produce a delay ranging from 20 ns to 100 ns, because of the large delay variation, it is necessary to use a variable charge pump current in the DDL, in order to guaranty stability for all the desired delay values. The electrical design of the circuit, in a 0.13-µm 1.2-V CMOS technology, will be presented, as well as electrical simulations results of the complete system.

Fast-settling low-power two-stage self-biased CMOS amplifier using feedforward-regulated cascode devices

Abstract: A fast-settling two-stage completely self-biased amplifier (op amp) is presented. The op amp uses two amplifying stages and feedforward-regulated cascode transistors to achieve high dc gain, while maintaining a reasonable output swing and high-frequency performance. Exhaustive simulation results over corners demonstrate that, after proper time-domain optimization of the proposed op amp in a 0.13-µm CMOS technology, a very fast settling with accuracy over 12 bits can be achieved, while dissipating very low power.