John Goodacre

TL;DR: The ARM reduced-instruction-set computing (RISC) processor has evolved to offer a family of chips that range up to a full-blown multiprocessor, and new chip designs could change how people access technology.

TL;DR: This work designs and implements a physical rack prototype and its liquid-cooling subsystem providing ultra-dense compute packaging, a storage architecture with distributed (in-node) non-volatile memory (NVM) devices, and a unified, low-latency interconnect, designed to efficiently uphold desired Quality-of-Service guarantees.

TL;DR: The EUROSERVER device will embed multiple silicon "chiplets" on an active silicon interposer, which is pioneering a system architecture approach that allows specialized silicon devices to be built even for low-volume markets where NRE costs are currently prohibitive.

TL;DR: The required processing performance of embedded processor core is getting higher and higher without increasing power consumption dramatically, and large SoC design has more risk of re-spin and long design time due to the complexity and difficulty of verification.

TL;DR: ECOSCALE introduces a novel heterogeneous energy-efficient hierarchical architecture, as well as a hybrid many-core+OpenCL programming environment and runtime system, aiming to substantially reduce energy consumption aswell as data traffic and latency.