Showing papers by "John W. Palmour published in 2018"
TL;DR: In this article, the authors have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE).
Abstract: High-energy neutrons produced by cosmic ray interactions with our atmosphere are known to cause single-event burnout (SEB) failure in power devices operating at high fields. We have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE). Comparing Wolfspeed SiC MOSFETs having different voltage (900V – 3300V) and current (3.5A – 72A) ratings, we find a universal behavior when scaling failure rates by active area, and scaling drain bias by avalanche voltage. Moreover, diodes and MOSFETs behave similarly, revealing that the SiC drift dominates the failure characteristics for both device types. This universal scaling holds for SiC MOSFETs from other manufacturers as well. The SEB characteristics of Si power IGBT and MOSFET devices show that near their rated voltages failure rates of Si devices can be 10X higher than that of comparable SiC MOSFET devices. Thus, Si devices are more susceptible to SEB failure from voltage overshoot conditions.
26 citations
TL;DR: In this paper, the effects of extended epitaxial defects on 4H-SiC power devices were explored, and the authors found that 3C inclusions and triangular defects, as well as heavily decorated substrate scratches, were device killing defects.
Abstract: This work explores the effects of extended epitaxial defects on 4H-SiC power devices. Advanced defect mapping techniques were used on large quantities of power device wafers, and data was aggregated to correlate device electrical characteristics to defect content. 1200 V class Junction Barrier Schottky (JBS) diodes and MOSFETs were examined in this manner; higher voltage 3.3 kV class devices were examined as well. 3C inclusions and triangular defects, as well as heavily decorated substrate scratches, were found to be device killing defects. Other defects were found to have negligible impacts on device yield, even in the case of extremely high threading dislocation content. Defect impacts on device reliability was explored on MOS-gate structures, as well as long-term device blocking tests on both MOSFETs and JBS diodes. Devices that passed on-wafer electrical parametric tests were found to operate reliably in these tests, regardless of defect content.
25 citations
TL;DR: In this paper, a 2-step lifetime enhancement process was introduced to move the roughness of the 4H-SiC surface to the lower E-field region of the device.
Abstract: An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO2, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O2 between amorphous SiO2 and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in VF over the 1300°C oxidized devices, without any impact on blocking characteristics.
5 citations
TL;DR: In this article, it was shown that the high voltage Ni/4H-SiC Schottky diodes with the dose Φ=(0.2-7)×1016cm-2 led to an increase in the base resistance, appearance of slow relaxation processes at extremely small currents, and increase of low frequency noise.
Abstract: Electron irradiation of high voltage Ni/4H-SiC Schottky diodes with the dose Φ=(0.2-7)×1016cm-2 led to increase in the base resistance, appearance of slow relaxation processes at extremely small currents, and increase of the low frequency noise. On exponential part of the current-voltage characteristics and on linear part of current-voltage characteristics in non-irradiated samples, low frequency noise always has the form of the 1/f noise. On linear part of the current-voltage characteristics in irradiated diodes the generation recombination (GR) noise predominates. Temperature dependences of the base resistivity and character of GR noise indicate that mainly Z1/2 center contributes to the change in the parameters of irradiated samples. Capture cross section of this level, obtained from noise measurements, is within the range (8×10-16-2×10-15) cm2 and only weakly depends on temperature.
TL;DR: In this article, a dual-side sintered power module with a low specific on-resistance (Rsp,on) of 1.8 mΩ⋅cm2 has been achieved on 650 V, 7 m Ω 4H-SiC DMOSFETs at 25°C.
Abstract: In this paper, we present our latest results on 650 V 4H-SiC DMOSFET developments for dual-side sintered power modules in electric drive vehicles. A low specific on-resistance (Rsp,on) of 1.8 mΩ⋅cm2 has been achieved on 650 V, 7 mΩ 4H-SiC DMOSFETs at 25°C, which increases to 2.4 mΩ⋅cm2 at 150°C. For the first time, the DMOSFET chip is designed specifically for use in dual-side soldering and sintering processes, and a 650 V, 1.7 mΩ SiC DMOSFET multichip half bridge power module has been built using the wirebond-free assembly. Compared to a similarly rated Si IGBT module, the conduction and switching losses were reduced by 80% and ~50%, respectively.