International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators

Organic field-effect transistors (OFETs) have been developed over the past few decades due to their potential applications in future electronics such as wearable and foldable electronics. As the electrical performance of OFETs has improved, patterning organic semiconducting crystals has become a key issue for their commercialization. However, conventional soft lithographic techniques have required the use of expensive processes to fabricate high-resolution master molds. In this study, we demonstrated a cost-effective method to prepare nanopatterned master molds for the fabrication of high-performance nanowire OFETs. We repurposed commercially available compact discs (CDs) as master molds because they already have linear nanopatterns on their surface. Flexible nanopatterned templates were replicated from the CDs using UV-imprint lithography. Subsequently, 6,13-bis-(triisopropylsilylethynyl) pentacene nanowires (NWs) were grown from the templates using a capillary force-assisted lithographic technique. The NW-based OFETs showed a high average field-effect mobility of 2.04 cm2 V−1 s−1. This result was attributed to the high crystallinity of the NWs and to their crystal orientation favorable for charge transport.

https://iopscience.iop.org/article/10.1088/1361-6528/aa6909/pdf

Repurposing compact discs as master molds to fabricate high-performance organic nanowire field-effect transistors

Models of threshold voltage and subthreshold slope (SS) for macaroni channel MOSFET are built for the first time based on the potential model in our previous work. These models clearly illustrate the variations of threshold voltage and subthreshold slope caused by short-channel-effects when changing gate length, silicon thickness, oxide thickness, channel doping concentration, and drain-to-source bias. The good agreements between simulations and models verified the validity of those models.

Models of Threshold Voltage and Subthreshold Slope for Macaroni Channel MOSFET

A method of designing a semiconductor circuit using a circuit simulation tool executed by a computer includes calculating power consumptions of elements of the semiconductor circuit by use of the circuit simulation tool. A thermal netlist is created about the semiconductor circuit, based on the power consumptions and geometry information of each of the elements. A simulation of the semiconductor circuit is performed with the thermal netlist using the circuit simulation tool to detect a temperature of each of the elements. The thermal netlist includes thermal capacitance information of each of the elements.

Simulation system estimating self-heating characteristic of circuit and design method thereof

We report the employment of an electrohydrodynamic-jet (EHD)-printed diketopyrrolopyrrole-based copolymer (P-29-DPPDTSE) as the active layer of fabricated organic field-effect transistors (OFETs) and circuits. The device produced at optimal conditions showed a field-effect mobility value of 0.45 cm2/(Vs). The morphologies of the printed P-29-DPPDTSE samples were determined by performing optical microscopy, X-ray diffraction, and atomic force microscopy experiments. In addition, numerical circuit simulations of the optimal printed P-29-DPPDTSE OFETs were done in order to observe how well they would perform in a high-voltage logic circuit application. The optimal printed P-29-DPPDTSE OFET showed a 0.5 kHz inverter frequency and 1.2 kHz ring oscillator frequency at a 40 V supply condition, indicating the feasibility of its use in a logic circuit application at high voltage.

Electrohydrodynamic-Jet (EHD)-Printed Diketopyrrolopyroole-Based Copolymer for OFETs and Circuit Applications.

As technology scales down, the impact of BEOL (Back-end of Line) interconnect resistance (R) and capacitance (C) on speed and power of digital circuits have been ever- increasing. Furthermore, in 3-D structured transistors, such as FinFETs and Nano-wire FETs, the parasitic R & C of MOL (Middle of Line) have larger impact on performance and power of the products. Hence, analysis of impact on variations of BEOL and MOL on parasitic component change is necessary. The conventional interconnect corner model uses extreme BEOL variations. However, the possibility of such extreme conditions occurring is stochastically very rare. Therefore, tightened corner models were proposed in order to reduce excessiveness in corner simulations. But this tightened corner models still have excessive ranges because each layer is statistically analyzed separately. In this study, we propose a circuit-level multi-layers aware BEOL corner (CMBC) based on Monte Carlo (MC) simulation of ring-oscillator circuits. This modeling methodology takes into account of both MOL process variations and multi-BEOL layers. As a result, the proposed corner model has a tighter distribution ranges of R & C. Therefore the proposed model allows circuit designers to reduce unnecessary efforts.

Jongwook Jeon

Papers

Repurposing compact discs as master molds to fabricate high-performance organic nanowire field-effect transistors

Models of Threshold Voltage and Subthreshold Slope for Macaroni Channel MOSFET

Simulation system estimating self-heating characteristic of circuit and design method thereof

Electrohydrodynamic-Jet (EHD)-Printed Diketopyrrolopyroole-Based Copolymer for OFETs and Circuit Applications.

Accurate BEOL statistical modeling methodology with circuit-level multi-layer process variations