International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators

In this paper, the thermal and electrical characteristics of a gate-all-around (GAA) vertical nanoplate-shaped field-effect transistor ( ${v}$ NPFET) are studied for sub-5-nm technologies using well-calibrated technology computer-aided design simulations. An asymmetric structure of a vertical device has different characteristics that depend on the source/drain position. When the source and the drain are placed at the top and the bottom electrodes, respectively, the GAA- ${v}$ NPFET drive current increases, but the self-heating effect becomes worse. To co-optimize the performance and the reliability, the gate delay ( $\tau _{\textsf {delay}}$ ) and the thermal resistance ( ${R}_{\textsf {th}}$ ) were evaluated simultaneously in terms of various geometric factors for the first time, showing that a reckless scaling of the channel thickness below 5 nm significantly degrades the electrothermal characteristics.

Analysis of Electrothermal Characteristics of GAA Vertical Nanoplate-Shaped FETs

In this paper, the structural and material optimization of gate sidewall spacer in the perspective of OFF-state leakage current was performed in a 3-nm node nanoplate FET (NPFET). Gate-induced drain leakage (GIDL) current, a dominant factor of OFF-state leakage current, and active performance (ON-current, ON/OFF current ratio, and dynamic performance) were co-optimized according to the structural correlation of gate sidewall spacer with other structural components such as gate, source, and drain length. By optimizing the structure for gate and spacer, intrinsic delay was improved by 9.8%, GIDL current was reduced by ~78%, and then on/off current ratio ( ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}})$ was enhanced by 4.2 times. On-current ( ${I}_{\mathrm{\scriptscriptstyle ON}}$ ) according to contact resistance ( ${R}_{\text {con}}$ ) and dynamic performance was analyzed in relation to source/drain (S/D) and spacer. Consequently, the intrinsic delay was improved by 10% and GIDL current reduced by about 92%, which enhanced ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ by 7.9 times accordingly. Furthermore, by comparing structural relations between gate spacer and S/D spacer, a better structural optimization method was proposed.

Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device

In this paper, we have devised on shallow trench isolation (STI) design considering leakage current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) in Bulk/silicon on insulator (SOI) FinFET and vertical FET (VFET). The ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ tendency is considered in terms of the interface trap density ( ${D}_{\textsf {it}}$ ) difference depending on the STI material type and STI thickness. In the case of Bulk FinFET, the STI design for each of high performance (HP) and low power (LP) is presented. On the other hand, in the case of SOI FinFET and VFET, STI designs which do not distinguish HP/LP are presented. Max lattice temperature ( ${T}_{\textsf {L,max}}$ )/thermal resistance ( ${R}_{\textsf {th}}$ )/on current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) degradation rate according to STI design in each structure are also analyzed. Finally, we compare the hot carrier injection (HCI)/bias temperature instability (BTI) lifetime as a function of the device temperature which is varied depending on STI design. In conclusion, our proposed STI design effectively reduces the self-heating effect in each structure and increases the HCI/BTI lifetime accordingly.

Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing ${I}_{OFF}$ in Various Sub-10-nm 3-D Transistors

Quinacridone-quinoxaline-based copolymer for organic field-effect transistors and its high-voltage logic circuit operations

In this paper, a closed form expression for noise parameters of MOSFETs are derived from a more accurate small-signal equivalent circuit. The modeling results show a good agreement with the measured data. Based on the analysis of the noise coming from channel thermal noise and parasitic resistances, the noise contribution from each component is analyzed.

Jongwook Jeon

Papers

Analysis of Electrothermal Characteristics of GAA Vertical Nanoplate-Shaped FETs

Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device

Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing ${I}_{OFF}$ in Various Sub-10-nm 3-D Transistors

Quinacridone-quinoxaline-based copolymer for organic field-effect transistors and its high-voltage logic circuit operations

A New Noise Parameter Model of Short-Channel MOSFETs