International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators

Due to the limitations of the currently widely used von Neumann architecture-based computing system, research on various devices and circuit systems suitable for logic-in-memory computing applications has been conducted. In this work, the silicon-based floating gate memory cell transistor structure, which has been attracting attention as a memory to replace the dynamic random access memory or NAND Flash technology, was newly recalled, and its applicability to logic-in-memory application was confirmed. This floating gate field effect transistor (FGFET) has the advantage that the compatibility of the existing silicon-based complementary metal–oxide–semiconductor (CMOS) process is far superior to that of logic-in-memory application devices to which materials with new memory characteristics are applied. At the 32 nm technology node, which is the front node to which the planar MOSFET structure is applied, an analysis environment that can simultaneously analyze the device and circuit of the FGFET was established. For a seamless connection between FGFET-based devices and circuit analysis, the compact model of the FGFET was developed, which is applied to logic-in-memory ternary content addressable memory (TCAM) circuit design. It was verified that the two types of logic-in-memory TCAM circuits to which FGFETs are applied are superior to a conventional CMOS FET-based TCAM circuit in the number of devices used (=circuit area) and power/energy efficiency.

Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

The design and measurement results of 3–5 GHz fully integrated ultra-wideband (UWB) CMOS LNA are presented. To boost the transconductance of the LNA and to reduce circuit area effectively, we eliminate a source degeneration inductor using resistive-feedback cascode structure. The implemented UWB LNA shows peak gain of 10.8 dB, more than 10 dB of input return loss, and a noise figure of 3.3–4.2 dB from 3 to 5.1 GHz with power dissipation of 14 mW. The input P1dB and input IP3 (IIP3) at 4 GHz are about −6 dBm and +4 dBm, respectively. For low cost, the LNA has been fabricated using a 0.18-μm thin metal CMOS process with top metal thickness of 0.84 μm. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 494–496, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24104

Low power size‐efficient CMOS UWB low‐noise amplifier design

In this paper, the channel thermal noise coefficient of Berkeley short-channel insulated gate field-effect transistor (IGFET) model 4 (BSIM4) is accurately extracted. To extract the noise coefficient of BSIM4, accurate channel thermal noise model was derived, which takes into account velocity saturation, channel length modulation, and carrier heating effects. Simplified short channel thermal noise model becomes a similar form with BSIM's channel thermal noise model which is based on the long-channel theory. From this result we presented the methodology for extraction of the channel thermal noise coefficient. We show the extracted noise coefficient of nanoscale RF metal?oxide?semiconductor field-effect transistor (MOSFET) with Leff = 21 nm.

http://iopscience.iop.org/article/10.1143/JJAP.48.04C037/pdf

Jongwook Jeon

Papers

Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

Low power size‐efficient CMOS UWB low‐noise amplifier design

Accurate Extraction of Excess Channel Thermal Noise Coefficient in Berkeley Short-Channel Insulated Gate Field-Effect Transistor Model 4

Investigation of Optimal Architecture of MoS2 Channel Field-Effect Transistors on a Sub-2 nm Process Node

Method for designing circuit using simulation tool estimating self-heating characteristic of circuit