A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P1dB of 10 to 12dBm, Psat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

An integrated SiGe superheterodyne RX/TX pair capable of Gb/s data rates in the 60GHz band is described. The 6dB NF RX includes an image-reject LNA, a multistage down-converter with on-chip IF filters, a frequency tripler, a PLL, and baseband outputs. The 10 to 12dBm P1dBTX achieves 10% PAE in the final stage. It includes a PA, image-reject driver, multistage up-converter with on-chip filters, tripler, and PLL

A silicon 60GHz receiver and transmitter chipset for broadband communications

The key issues for register file design in high-performance processors are access time and energy. While previous work has focused on reducing the number of registers, we propose to reduce the number of register ports through two proposals, one for reads and the other for writes. For reads, we propose bypass hint to reduce register port requirements by avoiding unnecessary register file reads for cases where values are bypassed. Current processors are unable to avoid these unnecessary reads due to timing constraints. For writes, we use register file banking. Current banking schemes assign different banks to instructions that are renamed together, which does not necessarily avoid conflicts among instructions that writeback together. We use decoupled rename, a technique which separates dependence and physical tagging of register operands. Decoupled rename allows us to perform physical register allocation just before writeback, avoiding bank conflicts. Our results show that combining bypass hint and write banking, our 1-cycle register file with 6 read ports, and two 4-write-ported banks achieves a 9% processor energy-delay savings over a system using a perfectly-pipelined, 2-cycle register file with 16 read ports and 8 write ports.

https://engineering.purdue.edu/~vijay/papers/2002/regfile.pdf

Reducing register ports for higher speed and lower energy

Defected ground structures (DGS) have been developed to improve characteristics of many microwave devices. Although the DGS has advantages in the area of themicrowave filter design, microwave oscillators, microwave couplers to increase the coupling, microwave amplifiers, etc., it is also used in the microstrip antenna design for different applications such as antenna size reduction, cross polarization reduction,mutual coupling reduction in antenna arrays, harmonic suppression etc., TheDGS ismotivated by a study of Photonic/Electromagnetic Band gap structures. The etching of one or more PBG element creates defect in the ground plane and used for the same purpose. The DGS is easy to be an equivalent L-C resonator circuit. The value of the inductance and capacitance depends on the area and size of the defect. By varying the various dimensions of the defect, the desired resonance frequency can be achieved. In this paper the effect of DGS, to the different antenna parameter enhancement is studied. Index Terms – Defected Ground Structure, Microstrip Antennas.

Defected Ground Structure in the perspective of Microstrip Antennas: A Review

In this paper, a new planar superstrate antenna concept suitable for integration with millimeter wave (mmWave) transceiver integrated circuits (ICs) is presented. The antenna is printed on the bottom of a dielectric superstrate with a ground plane below. The new design provides high bandwidth and high efficiency. Two different examples of the new concept have been designed and manufactured for the 60 GHz industrial scientific medical (ISM) band using folded dipoles. Simulated and measured input impedance matching and far field radiation patterns for both antennas will be shown and discussed. Both designs achieve over 10% bandwidth while maintaining better than 80% efficiency

Broadband Planar Superstrate Antenna for Integrated Millimeterwave Transceivers

In this paper, we describe an energy-efficient carry-lookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8 /spl mu/m CMOS technology, which included two 16-bit carry-lookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal.

A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems

We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-/spl mu/m CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V/sub dd/=3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at V/sub dd/=0.9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption.

/pdf/nmos-reversible-energy-recovery-logic-for-ultra-low-energy-4ae9xcgmul.pdf

nMOS reversible energy recovery logic for ultra-low-energy applications

A new ultra-wideband, low-loss and small-size coplanar waveguide (CPW) to coplanar strip (CPS) transition which can be used from DC to 110 GHz is presented. The proposed transition connects CPW with CPS by the reformed air-bridge. Two ground planes of CPW are tied at their ends by a line and the centre of the line is connected to the ground strip of CPS by another line. Owing to the symmetry of the proposed structure, the currents of two ground planes of CPW are combined with the same phase and transferred to the ground strip of CPS. With height of 3 /spl mu/m, the signal line of CPW passes over two connecting lines and is connected to the signal strip of CPS. For the back-to-back transition structure, insertion loss 15 dB are obtained from 0.5 to 110 GHz.

Ultra-wideband (from DC to 110 GHz) CPW to CPS transition

The authors propose a reversible energy recovery logic (RERL) circuit for ultra-low-energy consumption, which consumes only adiabatic energy loss and leakage current loss by completely eliminating non-adiabatic energy loss. It is a dual-rail adiabatic circuit using the concept of reversible logic with a new eight-phase clocking scheme. Simulation results show that at low-speed operation, the RERL consumes much less energy than the complementary static CMOS circuit and other adiabatic logic circuits.

Reversible energy recovery logic circuit without non-adiabatic energy loss

We proposed Reversible Energy Recovery Logic (RERL) using an 8-phase clocking scheme [1], which is a dualrail reversible adiabatic logic for ultra-low-energy applications. Because we eliminated non-adiabatic energy loss in RERL by using the concept of reversible logic, RERL has only adiabatic and leakage losses. In this paper we explain its operation and logic design and present its simulation and experimental results. We also present an energy-efficient 8-phase, clocked power generator that uses an off-chip inductor. With simulation results for the full adder, we confirmed that the RERL circuit consumed substantially less energy than other logic circuits at low-speed operation. We evaluated a test chip implemented with a 0.6-μm CMOS technology, which integrated a chain of inverters with a clocked power generator. In the experimental results, the RERL circuit consumed only 4.5% of the dissipated energy of a static CMOS circuit at an optimal operating speed of 40 kHz. In conclusion, RERL is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equal. key words: reversible logic, adiabatic circuit, clocked power

/pdf/reversible-energy-recovery-logic-circuits-and-its-8-phase-23y3wxqauh.pdf

Joonho Lim

Papers

A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems

nMOS reversible energy recovery logic for ultra-low-energy applications

Ultra-wideband (from DC to 110 GHz) CPW to CPS transition

Reversible energy recovery logic circuit without non-adiabatic energy loss

Reversible Energy Recovery Logic Circuits and Its 8-Phase Clocked Power Generator for Ultra-Low-Power Applications