Showing papers by "Jose Silva-Martinez published in 2013"

Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications

Abstract: A broadband CMOS direct-conversion receiver with on-chip frequency divider has been integrated in a 0.13- μm CMOS process. The key feature of the proposed receiver front-end is a single low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference and outstanding linearity. We employ a broadband common-gate (CG) LNTA with dual feedback to improve both gain and noise figure (NF) without breaking the fixed relationship between input impedance, transconductance gain, and load impedance. A LNTA load impedance boosting technique suppresses noise-amplification due to TIA, commonly found in passive mixers. The core circuit (RF and baseband signal path) consumes only 13 mW, and the prototype receiver achieves >22.4-dB conversion gain, dB NF, and ≥ -1.5 dBm IIP3 from 1.4 to 5.2 GHz. Maximum conversion gain of 24.3 dB and minimum NF of 6.5 dB are achieved at 1.4 and 2 GHz, respectively. The chip active area is 1.1 mm 2 with the entire RF signal path operated from a 1.2-V supply. The LO portion is biased from a 1.5-V supply.

A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

Abstract: A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode- based Charge Pump (CP) is proposed to minimize CP latency. The 5 G/10 G CDR prototype is fabricated in 0.18 μm CMOS technology to demonstrate the effectiveness of the proposed techniques for applications with high ratio of data-rate to ft. The proposed CDR recovers data with BER <; 2·10-13 and generates only 1.04 ps RMS and 7.5 ps peak-peak jitter. Jitter Tolerance (JTOL) test shows that the proposed CDR enhances low frequency jitter tracking and high frequency jitter filtering simultaneously for various jitter profiles. The CDR power consumption is 110.6 mW where only 3.9 mW is used for loop gain adaptation circuitry.

A 5-GHz CMOS LC Quadrature VCO With Dynamic Current-Clipping Coupling to Improve Phase Noise and Phase Accuracy

Abstract: This paper presents a quadrature voltage-controlled oscillator (QVCO) employing a proposed dynamic current-clipping coupling technique to provide around 90° phase shift in the coupling paths. The phase shift given by the coupling network not only improves the phase noise, but also desensitizes the phase error to component mismatches in the QVCO. The coupling network furthermore reduces the noise injected into the LC tank at the most vulnerable time (zero crossing points). The proposed current-clipping coupling allows the use of a strong coupling ratio to minimize the quadrature phase sensitivity to mismatches without degrading the phase noise performance. The proposed QVCO is implemented in a 130-nm CMOS technology. The measured phase noise is -121 dBc/Hz at 1-MHz offset from a 5-GHz carrier. The QVCO consumes 4.2 mW from a 1-V power supply, resulting in an outstanding figure of merit of 189 dBc/Hz.

A current-mode flash ADC for low-power continuous-time sigma delta modulators

Abstract: A current-mode flash analog-to-digital converter (ADC) with current summing stage was designed and evaluated. The topology is intended for low-power feed-forward continuous-time sigma delta (CTSD) modulators and was fabricated in a commercial 90nm CMOS technology. A 3-bit prototype has an effective number of bits (ENOB) of 2.87 bits at 2GS/s with 12MHz full-range input power. The static DNL and INL errors are both in the range of 0.24 LSB. The ADC achieves an SNDR of 15dB with a 1GHz input signal and an SNDR above 19dB for input signals below 300MHz. A major advantage of this architecture is its voltage scalability as well as the reduced input capacitance. The proposed ADC core dissipates 3.1mW power from a 1.2V supply while operating at 2GHz.

An external capacitor-less low drop-out regulator with superior PSR and fast transient response

Abstract: In this paper, an external capacitor-less low drop-out (LDO) voltage regulator with superior power supply rejection (PSR) and small transient ripple is described. The proposed LDO has the advantages of wide-band PSR and fast transient response while consuming only 18μA of quiescent current. Simulation results show that the LDO designed in a mainstream 0.18μm CMOS technology presents a PSR better than -55dB up to 1MHz when loaded by a 100pF capacitor. The peak-to-peak undershoots and overshoots are less than 75mV when load current pulses from 0 to 50mA with 1μs rise/fall times. Load regulation is around 30mV/mA and output voltage deflection is under 75mV when sweeping the load current in the range 0-50mA.

A 1.5 ns OFF/ON Switching-Time Voltage-Mode LVDS Driver/Receiver Pair for Asynchronous AER Bit-Serial Chip Grid Links With Up to 40 Times Event-Rate Dependent Power Savings

Abstract: This paper presents a low power fast ON/OFF switchable voltage mode implementation of a driver/receiver pair intended to be used in high speed bit-serial Low Voltage Differential Signaling (LVDS) Address Event Representation (AER) chip grids, where short (like 32-bit) sparse data packages are transmitted. Voltage-Mode drivers require intrinsically half the power of their Current-Mode counterparts and do not require Common-Mode Voltage Control. However, for fast ON/OFF switching a special high-speed voltage regulator is required which needs to be kept ON during data pauses, and hence its power consumption must be minimized, resulting in tight design constraints. A proof-of-concept chip test prototype has been designed and fabricated in low-cost standard 0.35 μm CMOS. At ±500 mV voltage swing with 500 Mbps serial bit rate and 32 bit events, current consumption scales from 15.9 mA (7.7 mA for the driver and 8.2 mA for the receiver) at 10 Mevent/s rate to 406 μA ( 343 μA for the driver and 62.5 μA for the receiver) for an event rate below 10 Kevent/s, therefore achieving a rate dependent power saving of up to 40 times, while keeping switching times at 1.5 ns. Maximum achievable event rate was 13.7 Meps at 638 Mbps serial bit rate. Additionally, differential voltage swing is tunable, thus allowing further power reductions.

Dual-Level Adaptive Supply Voltage System for Variation Resilience

Abstract: VLSI circuits of the 45-nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense, which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where the negative effect of variations is strong. We propose a dual-level ASV (dual-ASV) system for designs containing many timing critical paths. This system can simultaneously provide ASV at both coarse-grained and fine-grained levels, and has limited power routing overhead. The dual-ASV system is compared with conventional ASV through SPICE simulations on benchmark circuits. The results indicate that the dual-ASV system consumes significantly less power and achieves similar performance in the presence of variations.

Envelope tracking technique with bang-bang slew-rate enhancer for linear wideband RF PAs

Abstract: This paper deals with the design of power efficient switching regulators intended for linear power amplifiers employing envelope tracking techniques in wideband wireless standards. The bottlenecks in existing envelope tracking solutions involve a tradeoff between ripple voltage, slew rate and bandwidth. The slew rate limitation is identified as the main challenge and a `bang-bang' slew-enhancement technique is proposed for overcoming it. This approach enables the use of efficient supply modulators in wideband power amplifiers. The proposed scheme does not significantly degrade PA efficiency and improves the stability of the switching regulator. The prototype has been implemented using the TSMC 0.18 μm technology; schematic simulation results in Cadence® demonstrate the feasibility of the proposed technique.

Robust compensation scheme for low power capacitor-less low dropout voltage regulator

Abstract: With the expansion of battery powered mobile devices, power management has an ever increasing presence in the electronics industry. These devices require power management circuitry not only to extend the useful life of the battery but also to supply low noise voltage analog circuitry. The low-dropout voltage regulator (LDO) offers improved efficiency over other regulator topologies; however the architecture suffers from stability issues, which usually necessitates a large off-chip capacitor to ensure the regulator's performance. This work presents an alternative topology, removing the bulky external capacitor, thus allowing for greater power system integration. The proposed Current Amplifier Hybrid Compensation (CAHC) scheme implements an active feedback-feedforward compensation system and maintains both a fast transient response and full range alternating current (AC) stability from 0 to 50mA load currents even with a 100pF loading capacitance. The 1.2V External Capacitor-less LDO voltage regulator was designed and simulated in a commercial 0.35μm CMOS technology, and consumed only 61μA of quiescent current with a dropout voltage of less than 200mV. Simulated results demonstrate that the proposed External Capacitor-less LDO architecture overcomes the typical load transient and AC stability issues encountered in previous architectures. The combined size and component reduction of this architecture presents a more integrable and economic power management system.

Efficient calibration scheme for high-resolution pipelined ADCs

Abstract: This paper describes a background calibration technique that linearizes pipelined ADCs by correcting for errors in the digital domain. This also relaxes the requirements for the analog components and enables power and area savings. The calibration technique doesn't require a separate reference ADC that samples the input, nor the generation of digital correlation signals or extra analog calibration components. The calibration technique is robust and easily implementable in any digital technology. The implementation of the digital calibration algorithm requires minimal digital resources and less than 1% of the overall ADC power consumption.

Analog Baseband Filter Design Considerations for Wireless Receivers

Abstract: Design considerations applicable to analog baseband design for wireless receivers are discussed. Importance of out-of-band linearity and blocker tolerance requirements in analog filters is highlighted. A systematic analysis to evaluate the interdependence of analog baseband filter and a subsequent analog-to-digital converter (ADC) performance is presented. The analysis quantifies the effect of digital and analog modulated blockers on the design of the baseband filter specifications (order and approximation) and the ADC dynamic range. A cascaded, programmable, hybrid active-RC and switched capacitor low-pass filter suitable for a broadband UHF wireless receiver is illustrated as an example. Experimental results from the baseband filter and the prototype receiver are also included.

‘Bang-Bang’ technique in supply modulation for linear wideband RF power amplifiers

Abstract: This paper deals with the design techniques of power efficient switching regulators intended for linear power amplifiers employing envelope tracking techniques in wideband wireless standards. The bottlenecks involve a tradeoff between ripple voltage, slew rate and bandwidth. The slew rate limitation is identified as the main challenge, then a 'bang-bang' slew- enhancement technique is proposed. This approach enables the use of efficient supply modulators in wideband power amplifiers. The proposed scheme does not significantly degrade PA efficiency and preserves the stability of the switching regulator. The prototype has been implemented using the TSMC 0.18 µm technology; schematic simulation results in Cadence ®

Supply modulator for linear wideband RF power amplifiers

Abstract: Resumen Este articulo trata de las tecnicas de diseno de reguladores de potencia conmutados de alta eficiencia destinados a alimentar amplificadores de potencia (PAs) lineales, empleando tecnicas de seguimiento para estandares inalambricos de banda ancha. Los cuellos de botella presentados implican un compromiso entre tension, slew rate y ancho de banda. De hecho, la limitacion de slew rate es identificada como el principal desafio. Por tanto, se propone una tecnica de mejora del slew rate denominada “bang-bang”. Este enfoque permite el uso de moduladores de alimentacion eficientes para la alimentacion de los mencionado amplificadores de potencia de banda ancha. El esquema propuesto no degrada significativamente la eficiencia del PA y preserva, e incluso mejora, la estabilidad del regulador conmutado. El prototipo ha sido implementada utilizando la tecnologia de TSMC 0,18 µm. Resultados de simulacion post-layout en Cadence ® son presentados para demostrar la viabilidad del diseno llevado a cabo.

On-Chip SIDO Buck Converter with Independent Outputs

Abstract: The portable electronics market is rapidly migrating towards more compact devices requiring multiple high-integrity high-efficiency voltage supplies for empowering the systems. This paper demonstrates a single inductor used in a buck converter with two output voltages from an input battery with voltage of value 3 V. The main targets are low cross regulation between the two outputs to supply independent load current levels while maintaining desired output voltage values well within the acceptable ripple levels. The proposed controller provides adaptive levels in order to limit the output ripple, achieving a high output voltage accuracy. A reverse current detector to avoid negative current flowing through the inductor, prevents possible efficiency degradation.