Showing papers by "Jun Koyama published in 2013"
01 Jun 2013
TL;DR: IGZO-TFT LCD can realize lower power consumption and higher touch panel performance than a-Si TFT LCD and new LCD devices are reported on.
Abstract: Sharp succeeded the production of high performance LCD using IGZO for the first time in the world. With the extraordinary TFT characteristics, IGZO-TFT LCD can realize (1)lower power consumption and (2)higher touch panel performance than a-Si TFT LCD. In this paper, we report the development of IGZO-TFT and new LCD devices.
55 citations
17 Apr 2013
TL;DR: Good scalability of the processor in writing data to shadow memories and in area (5.7% overhead or less) is also confirmed through simulation and layout, based on flip-flops using 30-nm Si FETs combined with 0.3-μm CAAC-IGZO Fets which show good electronic characteristics and no overhead in area.
Abstract: A processor having a power management unit (PMU) and an 8-bit CPU including flip-flops with shadow memories is fabricated by 0.5-μm Si and 0.8-μm c-axis-aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO) technology. The shadow memories hold data without power supply utilizing low off-state current of CAAC-IGZO FETs. A break-even time (BET) of 4.9μs has been obtained. Good scalability of the processor in writing data to shadow memories and in area (5.7% overhead or less) is also confirmed through simulation and layout, based on flip-flops using 30-nm Si FETs combined with 0.3-μm CAAC-IGZO FETs which show good electronic characteristics and no overhead in area.
30 citations
26 May 2013
TL;DR: A 3bit/cell nonvolatile oxide semiconductor RAM (NOSRAM) test die comprising c-axis aligned crystal In-Ga-Zn-O TFTs has been fabricated.
Abstract: A 3bit/cell nonvolatile oxide semiconductor RAM (NOSRAM) test die comprising c-axis aligned crystal In-Ga-Zn-O TFTs has been fabricated. The write time of the test die is 100 ns. The test die collectively reads multilevel data within 900 ns with a 3bit A/D converter serving as reading circuit. The endurance of the 3bit/cell NOSRAM cell is more than 1012 cycles.
28 citations
TL;DR: It is revealed that suitable usages of positive and negative liquid crystals differ from each other according to their characteristics, which proves the possibility of reducing-eye-strain technology (REST) with reduced flickers.
Abstract: In order to reduce eye strain, a driving method for reducing flickers of liquid crystal display (LCD) is devised. For this driving, an oxide semiconductor (OS) is used in a backplane, liquid crystal and alignment layer materials are optimized, and a fringe field switching (FFS) mode with a structurally formed storage capacitor is used. This work reveals that suitable usages of positive and negative liquid crystals differ from each other according to their characteristics. This work also describes an OS-LCD with a touch sensor we fabricated for mobile devices, which proves the possibility of reducing-eye-strain technology (REST) with reduced flickers.
22 citations
28 Jun 2013
19 citations
01 Jun 2013
TL;DR: In this article, a method for extending an interval between data rewrite operations in displaying still images to various combinations of liquid crystal materials and alignment films, and confirmed that this method suppressed flickers in data rewriting.
Abstract: We applied a method for extending an interval between data rewrite operations in displaying still images to various combinations of liquid crystal materials and alignment films, and confirmed that this method suppressed flickers in data rewriting. Extending this interval during still image display will reduce eye strain.
18 citations
24 Oct 2013
TL;DR: In this paper, the authors focus on a very important feature of CAAC-IGZO FET, extremely low off-state current, and its pioneering various applications to LSI are reviewed and discussed.
Abstract: Crystalline In-Ga-Zn Oxide (IGZO) including c-axis aligned crystal (CAAC) enables FETs to show high reliability and extremely low off-state current. CAAC-IGZO technology is expected to grow to main technology of next-generation displays and is already contributing to mass-production of liquid crystal displays. In this paper by focusing on a very important feature of CAAC-IGZO FET, extremely low off-state current, its pioneering various applications to LSI are reviewed and discussed. In particular, a success in development of a hybrid process of CMOS FETs and CAAC-IGZO FETs promotes our developments of novel memories, processors, image sensors, and recently, field programmable gate arrays (FPGA).
14 citations
Patent•
29 May 2013
TL;DR: In this article, a power gate controller is used to stop the supply of power to the sensor and the CPU in the microcomputer in an interval between measurement periods, so that low power consumption can be achieved compared with the case where power is continuously supplied.
Abstract: In the microcomputer in the alarm device, supply of power to a sensor portion or a CPU in a sensor is allowed or stopped by a power gate controlled by a power gate controller. In addition, a volatile memory portion and a nonvolatile memory portion are provided in the CPU, data of the volatile memory portion is stored in the nonvolatile memory portion before supply of power to the CPU is stopped, and the data of the nonvolatile memory portion is restored to the volatile memory portion after the supply of power to the CPU is resumed. Thus, during an interval between measurement periods, supply of power to the sensor portion and the CPU can be stopped, so that low power consumption can be achieved compared with the case where power is continuously supplied.
11 citations
Patent•
18 Apr 2013
TL;DR: In this article, a power supply circuit includes a first switch, a voltage regulator circuit connected to the first switch and a control circuit for controlling the switch, which can reduce the power consumption of the power supply.
Abstract: A power supply circuit includes a first switch, a voltage regulator circuit connected to the first switch, and a control circuit for controlling the first switch. The control circuit includes a second switch, a third switch, and a voltage generation circuit. For controlling the first switch, first voltage output from the voltage generation circuit is applied to the first switch through the second switch, and second voltage output from the voltage generation circuit is applied to the first switch through the third switch. Power consumption of the power supply circuit can be reduced.
10 citations
TL;DR: In this paper, a state retention flip flop which retains its state without power, has zero area overhead, a theoretical zero backup time and simple power control was demonstrated in a Normally Off 32-bit CPU.
Abstract: A state retention flip flop which retains its state without power, has zero area overhead, a theoretical zero backup time and simple power control is demonstrated in a Normally-Off 32-bit CPU.
7 citations
01 Jun 2013
TL;DR: An OS‐LCD is fabricated, thereby revealing the possibility of reducing‐eye‐strain technology (REST) driving even in combination with a touch sensor, and a driving method reducing flickers is devised.
Abstract: In order to reduce eye strain, a driving method reducing flickers is devised. For this driving, material constitution is optimized and an FFS mode with a storage capacitor is used. We fabricated an OS-LCD, thereby revealing the possibility of reducing-eye-strain technology (REST) driving even in combination with a touch sensor.
TL;DR: In this article, a multi-context field-programmable gate array (FPGA) enabling fine-grained power gating (PG) is fabricated by a hybrid process involving a 1.0?m c-axis aligned crystalline In?Ga?Zn?O (CAAC-IGZO) field effect transistor (FET) and a 0.5?m complementary metal oxide semiconductor (CMOS) FET.
Abstract: A multi-context (MC) field-programmable gate array (FPGA) enabling fine-grained power gating (PG) is fabricated by a hybrid process involving a 1.0 ?m c-axis aligned crystalline In?Ga?Zn?O (CAAC-IGZO) field-effect transistor (FET), which is one of CAAC oxide-semiconductor (OS) FETs, and a 0.5 ?m complementary metal oxide semiconductor (CMOS) FET. The FPGA achieves a 20% layout area reduction in a routing switch and an 82.8% reduction in power required to retain data of configuration memory (CM) cells at 2.5 V driving compared to a static random access memory (SRAM)-based FPGA. A controller for fine-grained PG can be implemented at an area overhead of 7.5% per programmable logic element (PLE) compared to a PLE without PG. For each PLE, the power overhead with fine-grained PG amounts to 2.25 and 2.26 nJ for power-on and power-off, respectively, and break-even time (BET) is 19.4 ?s at 2.5 V and 10 MHz driving.
Patent•
20 May 2013
TL;DR: In this article, the authors proposed a power gate controlled power gate controller to reduce the power consumption of a microcomputer provided in an alarm apparatus, where the data of the nonvolatile storage unit is restored after the power supply to the CPU.
Abstract: PROBLEM TO BE SOLVED: To provide an alarm apparatus with power consumption reduced, and particularly an alarm apparatus in which the power consumption of a microcomputer provided therein is reduced.SOLUTION: In a microcomputer provided in an alarm apparatus, the power supply or the power stop for a CPU or a detection unit having a sensor is conducted by a power gate controlled by a power gate controller. Moreover, the CPU is provided with a volatile storage unit and a nonvolatile storage unit, and the data of the volatile storage unit are saved in the nonvolatile storage unit before stopping the power supply to the CPU and the data of the nonvolatile storage unit are restored in the volatile storage unit after the power supply to the CPU. Thus, the power supply to the CPU or the detection unit can be stopped between the measurement periods, whereby the power consumption can be reduced as compared with the case of supplying the power all the time.
Patent•
06 Aug 2013
TL;DR: In this article, the authors proposed a channel formation region in a semiconductor which has bandgap wider than that of silicon and an intrinsic carrier density lower than the one of silicon.
Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device driving method which reduces power consumption.SOLUTION: In a semiconductor device driving method, when a conducting state and a non-conducting state of an n-channel transistor and a p-channel transistor with gates being electrically connected with each other are switched during a first period, a switch for controlling electrical connection between first wiring and second wiring together with the n-channel transistor and the p-channel transistor is switched to a non-conducting state, and the switch is switched to the non-conducting state during a second period. The switch has a channel formation region in a semiconductor which has bandgap wider than that of silicon and an intrinsic carrier density lower than that of silicon.
Patent•
11 Jul 2013
TL;DR: In this paper, the problem of providing a driver circuit for a display device in which a lookup table can be written into a memory circuit within a retrace period even when the lookup table is frequently reconstructed in accordance with a change in the external environment and stored in the memory circuit, and data can be held even when supply of power supply voltage stops.
Abstract: PROBLEM TO BE SOLVED: To provide a driver circuit for a display device in which a lookup table can be written into a memory circuit within a retrace period even when the lookup table is frequently reconstructed in accordance with a change in the external environment and stored in the memory circuit, and data of the lookup table can be held even when supply of power supply voltage stops.SOLUTION: In a driver circuit for a display device, a memory circuit including a transistor having a semiconductor layer containing an oxide semiconductor is used as a memory circuit that stores a lookup table for correcting image signals in accordance with a change in the external environment.
Patent•
09 Apr 2013
TL;DR: In this paper, the problem of charge-up suppression in a transistor for use in a driving circuit part of a display device was addressed, where the wirings are partly or entirely not divided when the wires are formed.
Abstract: PROBLEM TO BE SOLVED: To suppress, in a transistor for use in a driving circuit part of a display device, charge-up in a gate wiring and a source wiring, thereby suppressing reduction in the yield caused by electrostatic destruction.SOLUTION: To suppress charge-up in a gate wiring and a source wiring, the wirings are partly or entirely not divided when the wirings are formed. Then, in a process of forming openings in a pixel part, openings reaching the wirings are prepared, and the openings are used to divide the wirings after finishing a transistor manufacturing process.