J
Jun Koyama
Researcher at Toshiba
Publications - 355
Citations - 9064
Jun Koyama is an academic researcher from Toshiba. The author has contributed to research in topics: Thin-film transistor & Display device. The author has an hindex of 46, co-authored 355 publications receiving 9020 citations.
Papers
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Patent
Control circuit and dc-dc converter
TL;DR: In this paper, a DC-DC converter with a hysteresis comparator, a logic unit, a digital-analog converter circuit, and a comparator is described.
Patent
Semiconductor film having a single-crystal like region with no grain boundary
TL;DR: In this article, a metal element which promotes crystallization of silicon is disposed in contact with a surface of the amorphous silicon film, and then a thermal processing is performed at a crystallization temperature of the polysilicon film or higher.
Patent
Display apparatus and method
TL;DR: In this article, a driving method was proposed to achieve high vertical resolution by starting a second field at a time point when writing of a first field has been completed, while information written in the first field is held.
Journal ArticleDOI
A normally-off microcontroller unit with an 85% power overhead reduction based on crystalline indium gallium zinc oxide field effect transistors
Kazuaki Ohshima,Hidetomo Kobayashi,Tatsuji Nishijima,Seiichi Yoneda,Hiroyuki Tomatsu,Shuhei Maeda,Kazuki Tsukida,Kei Takahashi,Takehisa Sato,Kazunori Watanabe,Ro Yamamoto,Munehiro Kozuma,Takeshi Aoki,Naoto Yamade,Yoshinori Ieda,Hidekazu Miyairi,Tomoaki Atsumi,Yutaka Shionoiri,Kiyoshi Kato,Yukio Maehashi,Jun Koyama,Shunpei Yamazaki +21 more
TL;DR: A low-power normally-off microcontroller unit (NMCU) having state-retention flip-flops using a c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as indium gallium zinc oxide (IGZO) transistors employing a distributed backup and recovery method (distributed method) is fabricated.
Patent
Semiconductor device and inverter circuit
TL;DR: In this article, the authors proposed a threshold control circuit for a plurality of TFTs, each having a back gate electrode, a semiconductor active layer, and a gate electrode provided in contact with the active layer through a second gate insulating film.