Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Nanowire Electronics: From Nanoscale to Macroscale

Silicon Quantum Electronics

Atomically thin two-dimensional (2D) materials belonging to transition metal dichalcogenides, due to their physical and electrical properties, are an exceptional vector for the exploration of next-generation semiconductor devices. Among them, due to the possibility of ambipolar conduction, tungsten diselenide (WSe2) provides a platform for the efficient implementation of polarity-controllable transistors. These transistors use an additional gate, named polarity gate, that, due to the electrostatic doping of the Schottky junctions, provides a device-level dynamic control of their polarity, that is, n- or p-type. Here, we experimentally demonstrate a complete doping-free standard cell library realized on WSe2 without the use of either chemical or physical doping. We show a functionally complete family of complementary logic gates (INV, NAND, NOR, 2-input XOR, 3-input XOR, and MAJ) and, due to the reconfigurable capabilities of the single devices, achieve the realization of highly expressive logic gates, suc...

Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors

2D nonlayered materials have attracted intensive attention due to their unique surface structure and novel physical properties. However, it is still a great challenge to realize the 2D planar structures of nonlayered materials owing to the naturally intrinsic covalent bonds. Ge is one of them with cubic structure impeding its 2D anisotropic growth. Here, the ultrathin single-crystalline Ge flakes as thin as 8.5 nm were realized via halide-assisted self-limited CVD growth. The growth mechanism has been confirmed by experiments and theoretical calculations, which can be attributed to the preferential growth of the (111) plane with the lowest formation energy and the giant interface distortion effect of the Cl–Ge motif. Excitingly, a Ge flake-based phototransistor shows excellent performances such as a high hole mobility of ∼263 cm2 V–1 s–1, a high responsivity of ∼200 A/W, and fast response rates (τrise = 70 ms, τdecay = 6 ms), suggesting its great potential in the applications of electronics and optoelectr...

Halide-Induced Self-Limited Growth of Ultrathin Nonlayered Ge Flakes for High-Performance Phototransistors

Germanium is a promising material for future very large scale integration transistors, due to its superior hole mobility. However, germanium-based devices typically suffer from high reverse junction leakage due to the low band-gap energy of 0.66 eV and therefore are characterized by high static power dissipation. In this paper, we experimentally demonstrate a solution to suppress the off-state leakage in germanium nanowire Schottky barrier transistors. Thereto, a device layout with two independent gates is used to induce an additional energy barrier to the channel that blocks the undesired carrier type. In addition, the polarity of the same doping-free device can be dynamically switched between p- and n-type. The shown germanium nanowire approach is able to outperform previous polarity-controllable device concepts on other material systems in terms of threshold voltages and normalized on-currents. The dielectric and Schottky barrier interface properties of the device are analyzed in detail. Finite-element...

Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions

In this work, we investigate the temperature dependence of electrical switching properties of back-gated, undoped Si-nanowire field-effect transistors with Ni-silicided source/drain contacts. A simple, phenomenological model illustrates the leading order temperature dependence of the source-drain current, which originates predominantly from charge carrier injection by tunneling through the Schottky junction. Drain current versus gate voltage measurements have been performed for various temperatures and several drain voltages on a single nanowire device. The temperature dependence of the drain-source current for specific gate and drain voltages is analysed within the framework of voltage dependent effective barrier heights. As a result, the temperature dependence of the tunnelling current is not only important for the sub-threshold region, but also plays a significant role in the transistor “on-state”. In addition, the effective barrier heights for electrons and holes tend towards the natural Schottky barriers of the NiSi2-Si interface, if the applied external fields generate the case of flat band condition at the injection Schottky barrier, i.e. in the deep “off-state” region. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

/pdf/temperature-dependent-switching-behaviour-of-nickel-3kqoy0cm8r.pdf

Temperature dependent switching behaviour of nickel silicided undoped silicon nanowire devices

In this paper, we present mobility investigations of strained nMOS and pMOS short-channel transistors with dimensions down to 30-nm gate length. Using the geometrical magnetoresistance (MR) effect, carrier mobility of electrons and holes in the inversion channel of a recent state-of-the-art CMOS technology is presented from linear to saturation operation conditions. The MR effect allows for a more direct access to the carrier mobility compared with the conventional current/voltage and capacitance/voltage mobility derivation methods, in which series resistance, inversion charge density, and effective channel length are necessary to extract the mobility values of the short-channel devices. In another way, the MR effect can help to disentangle the performance gain of the strained state-of-the art devices to changes in channel mobility or device connection, e.g., series resistance effects.

Mobility Investigations on Strained 30-nm High- $k$ Metal Gate MOSFETs by Geometrical Magnetoresistance Effect

Silicon has dominated the microelectronics industry for the last 50 years. With its zero nuclear spin isotope (28Si) and low spin orbit coupling, it is believed that silicon can become an excellent host material for an entirely new generation of devices that operate under the laws of quantum mechanics [1}. Semiconductor nanowires however, offer huge potential as the next building blocks of nano-devices due to their one-dimensional structure and properties [2]. We describe a fabrication process to prepare doped vapor-liquid-solid (VLS) grown silicon nanowire samples in a 2- and 4-terminal measurement setup for electrical characterisation.

Jurgen Beister

Papers

Enabling Energy Efficiency and Polarity Control in Germanium Nanowire Transistors by Individually Gated Nanojunctions

Temperature dependent switching behaviour of nickel silicided undoped silicon nanowire devices

Mobility Investigations on Strained 30-nm High- $k$ Metal Gate MOSFETs by Geometrical Magnetoresistance Effect

Development Of nanowire devices with quantum functionalities