International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Solid-state electronics

Japanese journal of applied physics : JJAP online.

We propose the use of a high-κ spacer to improve the electrostatic integrity and, thereby, the scalability of silicon junctionless transistors (JLTs) for the first time. Using extensive simulations of n-channel JLTs, we demonstrate that the high-κ spacers improve the electrostatic integrity of JLTs at sub-22-nm gate lengths. Electric field that fringes through the high-κ spacer to the device layer on either sides of the gate results in an effective increase in electrical gate length in the off-state. However, the effective gate length is unaffected in the on-state. Hence, the off-state leakage current is reduced by several orders of magnitude with the use of a high-κ spacer with concomitent improvements in the subthreshold swing and drain-induced barrier lowering. A marginal improvement in the on-state current is observed with the use of the high-κ spacer, and this is related to the reduction in parasitic resistance in the silicon under the spacer due to fringe fields.

Enhanced Electrostatic Integrity of Short-Channel Junctionless Transistor With High- $\kappa$ Spacers

Organic-inorganic hybrid perovskite solar cells (PSCs) have seen a rapid rise in power conversion efficiencies in recent years; however, they still suffer from interfacial recombination and charge extraction losses at interfaces between the perovskite absorber and the charge-transport layers. Here, in situ back-contact passivation (BCP) that reduces interfacial and extraction losses between the perovskite absorber and the hole transport layer (HTL) is reported. A thin layer of nondoped semiconducting polymer at the perovskite/HTL interface is introduced and it is shown that the use of the semiconductor polymer permits-in contrast with previously studied insulator-based passivants-the use of a relatively thick passivating layer. It is shown that a flat-band alignment between the perovskite and polymer passivation layers achieves a high photovoltage and fill factor: the resultant BCP enables a photovoltage of 1.15 V and a fill factor of 83% in 1.53 eV bandgap PSCs, leading to an efficiency of 21.6% in planar solar cells.

In Situ Back-Contact Passivation Improves Photovoltage and Fill Factor in Perovskite Solar Cells.

We report a twin gate tunnel field effect transistor-based capacitorless dynamic memory with improved retention characteristics through well-calibrated simulations. The first front gate of the twin gate architecture regulates the read mechanism based on band-to-band tunneling whereas the second front gate creates and maintains a dedicated volume for the charge storage near the drain region. The profound well along with the optimized bias values aid to attain a retention time ( RT ) of $\sim 1.5$ s at 85 °C. Systematic analysis shows that the storage region can be scaled down to 50 nm with further improvement in RT by using an underlap region between drain and second gate. Optimally designed twin gate device exhibits an improved RT at higher temperature (125 °C).

Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism

In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ∼2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory.

Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

This paper presents a one-transistor dynamic random access memory (1T-DRAM) based on a novel surrounding-gate transistor with wide trenched body (WT-SGT). This 1T-DRAM exhibits favorable transient performance after word line (WL)/bit line (BL) disturbance, which is verified using Sentaurus TCAD 12.0. The proposed memory cell can be fabricated with a feature area of 4 $\mathrm{F}^{2 }$ and with processes that are fully compatible with conventional CMOS technology. Extended simulations reveal three key findings. First, the WT-SGT achieves a high-speed programming operation (1.17 ns) at a low operating voltage (1.6 V) and with a programming window that can be further extended by widening its trenched body. Second, the recombination rate is also reduced, thereby yielding an acceptable retention time (RT) of 625.6 ms. Third, the decreased RT after a 100-ns WL/BL disturbance is improved by 33%, as compared with a conventional SGT 1T-DRAM. We, therefore, believe that this new device will become a competitive candidate for use in future DRAM cells.

Transient and Thermal Analysis on Disturbance Immunity for 4 $\mathrm{F}^{2}$ Surrounding Gate 1T-DRAM With Wide Trenched Body

A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time.

Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure

To investigate the effect of surface texturing for high-efficiency heterojunction with intrinsic thin layer (HIT) solar cells, we have systematically designed different textures and numerically evaluated their ability to trap light. These evaluations were first calibrated by physically fabricating a general pyramid-structured HIT solar cell. The performance of various textures is compared, such as a flat structure, a pillar structure, and different types of pyramid and inverse pyramid structures. Simulation results identify the pillar structure as the best, because the light is reflected several times onto the surface, so that more of the light is trapped by the substrate. The pillar structure HIT solar cell's conversion efficiency of 25.73% is an improvement over the 24.7% of the conventional random pyramid HIT solar cell.

Jyi-Tsong Lin

Papers

Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism

Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

Transient and Thermal Analysis on Disturbance Immunity for 4 $\mathrm{F}^{2}$ Surrounding Gate 1T-DRAM With Wide Trenched Body

Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure

A High-Efficiency HIT Solar Cell With Pillar Texturing