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Chi-Chun Chen
Researcher at National Chiao Tung University
Publications - 20
Citations - 696
Chi-Chun Chen is an academic researcher from National Chiao Tung University. The author has contributed to research in topics: Gate oxide & Gate dielectric. The author has an hindex of 9, co-authored 20 publications receiving 673 citations. Previous affiliations of Chi-Chun Chen include TSMC.
Papers
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Proceedings ArticleDOI
5nm-gate nanowire FinFET
Fu-Liang Yang,Di-Hong Lee,Hou-Yu Chen,Chang-Yun Chang,Sheng-Da Liu,Cheng-Chuan Huang,Tang-Xuan Chung,Hung-Wei Chen,Chien-Chao Huang,Yi-Hsuan Liu,C.C. Wu,Chi-Chun Chen,Shih-Chang Chen,Ying-Tsung Chen,Ying-Ho Chen,C.H. Chen,Bor-Wen Chan,Peng-Fu Hsu,Jyu-Horng Shieh,Han-Jan Tao,Yee-Chia Yeo,Yiming Li,Jam-Wem Lee,Pu Chen,Mong-Song Liang,Chenming Hu +25 more
TL;DR: In this paper, a new nanowire FinFET structure was developed for CMOS device scaling into the sub-10 nm regime, and gate delay of 0.22 and 0.48 ps with excellent sub-threshold characteristics were achieved with very low off leakage cur-rent less than 10 nA/ /spl mu/m.
Proceedings ArticleDOI
25 nm CMOS Omega FETs
Fu-Liang Yang,Hao-Yu Chen,Fang-Cheng Chen,Cheng-Chuan Huang,Chang-Yun Chang,Chiu Hsien-Kuang,Chi-Chuang Lee,Chi-Chun Chen,Huan-Tsung Huang,C.H. Chen,Hun-Jan Tao,Yee-Chia Yeo,Mong-Song Liang,Chenming Hu +13 more
TL;DR: In this paper, low leakage and low active power 25 nm gate length C-MOSFETs are demonstrated for the first time with a newly proposed Omega-(/spl Omega/) shaped structure, at a conservative 17-19 /spl Aring/ gate oxide thickness, and with excellent hot carrier immunity.
Patent
Dual-gate structure and method of fabricating integrated circuits having dual-gate structures
TL;DR: In this paper, a method of fabricating a dual-gate on a substrate and an integrated circuit having a dualgate structure is provided, where a first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area for a second gate structure.
Journal ArticleDOI
Evaluation of plasma charging damage in ultrathin gate oxides
Horng-Chih Lin,Chi-Chun Chen,Chao-Hsing Chien,Szu-Kang Hsein,Meng-Fan Wang,Tien-Sheng Chao,Tiao-Yuan Huang,Chun-Yen Chang +7 more
TL;DR: In this article, it was observed that the shift of several device parameters, including threshold voltage, transconductance, and subthreshold swing, are not sensitive to plasma charging and thus not suitable for this purpose.
Proceedings ArticleDOI
Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography
Hou-Yu Chen,Chang-Yun Chang,Chien-Chao Huang,Tang-Xuan Chung,Sheng-Da Liu,Jiunn-Ren HwangYi-Hsuan Liu,Yu-Jun Chou,Hong-Jang Wu,King-Chang Shu,Chung-Kan Huang,Jan-Wen You,Jaw-Jung Shin,Chun-Kuang Chen,Chia-Hui Lin,Ju-Wang Hsu,Bao-Chin Perng,Pang-Yen Tsai,Chi-Chun Chen,Jyu-Horng Shieh,Han-Jan Tao,Shin-Chang Chen,Tsai-Sheng Gau,Fu-Liang Yang +22 more
TL;DR: In this article, a hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm SiON gate dielectric has been developed for advanced SOC applications.