K
K. Byon
Researcher at Intel
Publications - 1
Citations - 71
K. Byon is an academic researcher from Intel. The author has contributed to research in topics: NMOS logic & PMOS logic. The author has an hindex of 1, co-authored 1 publications receiving 65 citations.
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A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products
C.-H. Jan,F. Al-Amoody,Chang Hsu-Yu,Tsung-Yuan Chang,Y.-W. Chen,N. L. Dias,Hafez Walid M,D. Ingerly,M. Jang,Eric Karl,S. K.-Y. Shi,K. Komeyli,H. Kilambi,A. Kumar,K. Byon,Chen-Guan Lee,J. Lee,T. Leo,Pei-Chi Liu,Nidhi Nidhi,Olac-Vaw Roman W,C. Petersburg,K. Phoa,Chetan Prasad,C. Quincy,Ramaswamy Rahul,T. Rana,L. Rockford,Anand Subramaniam,Curtis Tsai,P. Vandervoorn,L. Yang,A. Zainuddin,P. Bai +33 more
TL;DR: A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology has been optimized for density, low power and wide dynamic range and a full suite of analog, mixed-signal and RF features are supported.