P
Pei-Chi Liu
Researcher at Intel
Publications - 5
Citations - 89
Pei-Chi Liu is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Gate dielectric. The author has an hindex of 3, co-authored 5 publications receiving 83 citations.
Papers
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Proceedings ArticleDOI
A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products
C.-H. Jan,F. Al-Amoody,Chang Hsu-Yu,Tsung-Yuan Chang,Y.-W. Chen,N. L. Dias,Hafez Walid M,D. Ingerly,M. Jang,Eric Karl,S. K.-Y. Shi,K. Komeyli,H. Kilambi,A. Kumar,K. Byon,Chen-Guan Lee,J. Lee,T. Leo,Pei-Chi Liu,Nidhi Nidhi,Olac-Vaw Roman W,C. Petersburg,K. Phoa,Chetan Prasad,C. Quincy,Ramaswamy Rahul,T. Rana,L. Rockford,Anand Subramaniam,Curtis Tsai,P. Vandervoorn,L. Yang,A. Zainuddin,P. Bai +33 more
TL;DR: A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology has been optimized for density, low power and wide dynamic range and a full suite of analog, mixed-signal and RF features are supported.
Patent
Transistor gate metal with laterally graduated work function
Chia-Hong Jan,Hafez Walid M,Chang Hsu-Yu,Olac-Vaw Roman W,Chang Ting,Ramaswamy Rahul,Pei-Chi Liu,N. L. Dias +7 more
TL;DR: In this paper, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance, and a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness.
Patent
Mos antifuse with void-accelerated breakdown
Olac-Vaw Roman W,Hafez Walid M,Chia-Hong Jan,Chang Hsu-Yu,Chang Ting,Ramaswamy Rahul,Pei-Chi Liu,N. L. Dias +7 more
TL;DR: In this paper, a MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode is presented, where the programming voltage at which the MOS anti-antifuse undergoes deformation is reduced through intentional damage.
Patent
Non-linear fin-based devices
N. L. Dias,Chia-Hong Jan,Hafez Walid M,Olac-Vaw Roman W,Chang Hsu-Yu,Chang Ting,Ramaswamy Rahul,Pei-Chi Liu +7 more
TL;DR: In this article, a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other is described. But the major axes of the first and second portions are not co-collinear.
Patent
Compound lateral resistor structures for integrated circuitry
TL;DR: In this paper, a lateral compound resistive trace is constructed by replacing a portion of a first resistive material along the centerline of the resistive traces with a second resistive component, so that the second component is embedded within the first component.