Atomic layer deposition (ALD) is gaining attention as a thin film deposition method, uniquely suitable for depositing uniform and conformal films on complex three-dimensional topographies. The deposition of a film of a given material by ALD relies on the successive, separated, and self-terminating gas–solid reactions of typically two gaseous reactants. Hundreds of ALD chemistries have been found for depositing a variety of materials during the past decades, mostly for inorganic materials but lately also for organic and inorganic–organic hybrid compounds. One factor that often dictates the properties of ALD films in actual applications is the crystallinity of the grown film: Is the material amorphous or, if it is crystalline, which phase(s) is (are) present. In this thematic review, we first describe the basics of ALD, summarize the two-reactant ALD processes to grow inorganic materials developed to-date, updating the information of an earlier review on ALD [R. L. Puurunen, J. Appl. Phys. 97, 121301 (2005)], and give an overview of the status of processing ternary compounds by ALD. We then proceed to analyze the published experimental data for information on the crystallinity and phase of inorganic materials deposited by ALD from different reactants at different temperatures. The data are collected for films in their as-deposited state and tabulated for easy reference. Case studies are presented to illustrate the effect of different process parameters on crystallinity for representative materials: aluminium oxide, zirconium oxide, zinc oxide, titanium nitride, zinc zulfide, and ruthenium. Finally, we discuss the general trends in the development of film crystallinity as function of ALD process parameters. The authors hope that this review will help newcomers to ALD to familiarize themselves with the complex world of crystalline ALD films and, at the same time, serve for the expert as a handbook-type reference source on ALD processes and film crystallinity.

Crystallinity of inorganic films grown by atomic layer deposition: Overview and general trends

Electrochemical energy storage technology is of critical importance for portable electronics, transportation and large-scale energy storage systems. There is a growing demand for energy storage devices with high energy and high power densities, long-term stability, safety and low cost. To achieve these requirements, novel design structures and high performance electrode materials are needed. Porous 1D nanomaterials which combine the advantages of 1D nanoarchitectures and porous structures have had a significant impact in the field of electrochemical energy storage. This review presents an overview of porous 1D nanostructure research, from the synthesis by bottom-up and top-down approaches with rational and controllable structures, to several important electrochemical energy storage applications including lithium-ion batteries, sodium-ion batteries, lithium-sulfur batteries, lithium-oxygen batteries and supercapacitors. Highlights of porous 1D nanostructures are described throughout the review and directions for future research in the field are discussed at the end.

Porous One-Dimensional Nanomaterials: Design, Fabrication and Applications in Electrochemical Energy Storage.

Atomic layer deposition (ALD) is a thin film technology that in the past two decades rapidly developed from a niche technology to an established method. It proved to be a key technology for the surface modification and the fabrication of complex nanostructured materials. In this Progress Report, after a short introduction to ALD and its chemistry, the versatility of the technique for the fabrication of novel functional materials will be discussed. Selected examples, focused on its use for the engineering of nanostructures targeting applications in energy conversion and storage, and on environmental issues, will be discussed. Finally, the challenges that ALD is now facing in terms of materials fabrication and processing will be also tackled.

Atomic Layer Deposition of Nanostructured Materials for Energy and Environmental Applications

The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

A comprehensive review on emerging artificial neuromorphic devices

In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.

The era of hyper-scaling in electronics

We fabricate, characterize, and establish the critical design criteria of Hf0.5Zr0.5O2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application. We quantify ${V}_{\textsf {TH}}$ shift from electron (hole) trapping in the vicinity of ferroelectric (FE)/interlayer (IL) interface, induced by erase (program) pulse, and ${V}_{\textsf {TH}}$ shift from polarization switching to determine true memory window (MW). The devices exhibit extrapolated retention up to 10 years at 85 °C and endurance up to $5\times 10^{6}$ cycles initiated by the IL breakdown. Endurance up to 1012 cycles of partial polarization switching is shown in metal–FE–metal capacitor, in the absence of IL. A comprehensive metal–FE–insulator–semiconductor FeFET model is developed to quantify the electric field distribution in the gate-stack, and an IL design guideline is established to markedly enhance MW, retention characteristics, and cycling endurance.

Critical Role of Interlayer in Hf 0.5 Zr 0.5 O 2 Ferroelectric FET Nonvolatile Memory Performance

This paper presents an overview and perspective on processing technologies required for continued scaling of leading edge and emerging semiconductor devices. We introduce the main drivers and trends affecting future semiconductor device scaling and provide examples of emerging devices and architectures that may be implemented within the next 10-20 yr. We summarize multiple active areas of research to explain how future thin film deposition, etch, and patterning technologies can enable 3D (vertical) power, performance, area, and cost scaling. Emerging and new process technologies will be required to enable improved contacts, scaled and future devices and interconnects, monolithic 3D integration, and new computing architectures. These process technologies are explained and discussed with a focus on opportunities for continued improvement and innovation.

Perspective: New process technologies required for future devices and scaling

The challenges of reducing gate leakage current and dielectric breakdown beyond the 45 nm technology node have shifted engineers' attention from the traditional and proven dielectric SiO 2 to materials of higher dielectric constant also known as high-k materials such as hafnium oxide (HfO 2 ) and aluminum oxide (Al 2 O 3 ). These high-k materials are projected to replace silicon oxide (SiO 2 ). In order to address the complex process integration and reliability issues, it is important to investigate the mechanical properties of these dielectric materials in addition to their electrical properties. In this study, HfO 2 and Al 2 O 3 have been fabricated using atomic layer deposition (ALD) on (100) p-type Si wafers. Using nanoindentation and the continuous stiffness method, we report the elastomechanical properties of HfO 2 and Al 2 O 3 on Si. ALD HfO 2 thin films were measured to have a hardness of 9.5 ± 2 GPa and a modulus of 220 ± 40 GPa, whereas the ALD Al 2 O 3 thin films have a hardness of 10.5 ± 2 GPa and a modulus of 220 ± 40 GPa. The two materials are also distinguished by very different interface properties. HfO 2 forms a hafnium silicate interlayer, which influences its nanoindentation properties close to the interface with the Si substrate, while Al 2 O 3 does not exhibit any interlayer.

https://www.fpl.fs.fed.us/documnts/pdf2008/fpl_2008_tapily001.pdf

Nanoindentation Investigation of HfO2 and Al2O3 Films Grown by Atomic Layer Deposition

We report, for the first time, a gate last process, used to fabricate Negative Capacitance field effect transistors (NCFETs) with Hf 0.5 Zr 0.5 O 2 (HZO) as ferroelectric (FE) dielectric in a metal/ferroelectric/insulator/semiconductor (MFIS) configuration. Long channel NCFET's with HZO thickness down to 5 nm exhibit consistent switching behavior with switching slope (SS rev ) below kT/q over four decades of drain current. Temperature dependent transport study shows that, the effective mobility of HZO NCFETs is 15 % higher than that of HfO 2 based control MOSFETs due to suppression of Hf diffusion into the interfacial SiO 2 layer (IL). Using the Preisach hysteresis model, which models dynamics of FE switching through a cluster of independent switching dipoles at arbitrary electric field, we (a) explain the asymmetric SS behavior of NCFETs in MFIS configuration, and (b) establish design guidelines for achieving sub-kT/q SS in both forward and reverse sweep direction.

Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack

According to one embodiment of the invention, a method is provided for selective surface deposition. In one example, the method includes providing a substrate containing a first material having a first surface and a second material having a second surface, forming a modified first surface and a modified second surface by exposing the first surface and the second surface to hydrogen gas excited by a plasma source, and selectively depositing a film on the modified second surface but not on the modified first surface.

Kandabara Tapily

Papers

Critical Role of Interlayer in Hf 0.5 Zr 0.5 O 2 Ferroelectric FET Nonvolatile Memory Performance

Perspective: New process technologies required for future devices and scaling

Nanoindentation Investigation of HfO2 and Al2O3 Films Grown by Atomic Layer Deposition

Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack

Method of selective gas phase film deposition on a substrate