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Pankaj Sharma

Researcher at University of Notre Dame

Publications -  21
Citations -  1322

Pankaj Sharma is an academic researcher from University of Notre Dame. The author has contributed to research in topics: Graphene & Field-effect transistor. The author has an hindex of 14, co-authored 21 publications receiving 887 citations. Previous affiliations of Pankaj Sharma include École Polytechnique Fédérale de Lausanne & École Normale Supérieure.

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Proceedings ArticleDOI

Ferroelectric FET analog synapse for acceleration of deep neural network training

TL;DR: A transient Presiach model is developed that accurately predicts minor loop trajectories and remnant polarization charge for arbitrary pulse width, voltage, and history of FeFET synapses and reveals a 103 to 106 acceleration in online learning latency over multi-state RRAM based analog synapses.
Journal ArticleDOI

Critical Role of Interlayer in Hf 0.5 Zr 0.5 O 2 Ferroelectric FET Nonvolatile Memory Performance

TL;DR: In this paper, the critical design criteria of Hf0.5Zr 0.5O2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application were established.
Journal ArticleDOI

Non-contact characterization of graphene surface impedance at micro and millimeter waves

TL;DR: In this paper, the surface impedance of monolayer graphene at micro and millimeter wave frequencies is characterized using the transmission matrices of a rectangular waveguide, which is based on a simple lumped element in a transmission line model that exactly represents the electromagnetic problem under study.
Journal ArticleDOI

A ferroelectric field effect transistor based synaptic weight cell

TL;DR: In this paper, the voltage-controlled partial polarization switching dynamics in ferroelectric-field-effect transistors (FeFETs) are harnessed to enable a 32 state nonvolatile analog synaptic weight cell with large dynamic range (67×) and low latency weight updates (50 ns) for an amplitude modulated pulse scheme.
Proceedings ArticleDOI

Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack

TL;DR: In this paper, a gate last process was used to fabricate Negative Capacitance field effect transistors (NCFETs) with Hf 0.5 Zr 0.5 O 2 (HZO) dielectric in a metal/ferroelectric/insulator/semiconductor (MFIS) configuration.