Parallel processes for patterning densely packed nanometre-scale structures are critical for many diverse areas of nanotechnology. Thin films of diblock copolymers can self-assemble into ordered periodic structures at the molecular scale (approximately 5 to 50 nm), and have been used as templates to fabricate quantum dots, nanowires, magnetic storage media, nanopores and silicon capacitors. Unfortunately, perfect periodic domain ordering can only be achieved over micrometre-scale areas at best and defects exist at the edges of grain boundaries. These limitations preclude the use of block-copolymer lithography for many advanced applications. Graphoepitaxy, in-plane electric fields, temperature gradients, and directional solidification have also been demonstrated to induce orientation or long-range order with varying degrees of success. Here we demonstrate the integration of thin films of block copolymer with advanced lithographic techniques to induce epitaxial self-assembly of domains. The resulting patterns are defect-free, are oriented and registered with the underlying substrate and can be created over arbitrarily large areas. These structures are determined by the size and quality of the lithographically defined surface pattern rather than by the inherent limitations of the self-assembly process. Our results illustrate how hybrid strategies to nanofabrication allow for molecular level control in existing manufacturing processes.

Epitaxial self-assembly of block copolymers on lithographically defined nanopatterned substrates

Enabling nanotechnology with self assembled block copolymer patterns

Methods to pattern substrates with dense periodic nanostructures that combine top-down lithographic tools and self-assembling block copolymer materials are provided. According to various embodiments, the methods involve chemically patterning a substrate, depositing a block copolymer film on the chemically patterned imaging layer, and allowing the block copolymer to self-assemble in the presence of the chemically patterned substrate, thereby producing a pattern in the block copolymer film that is improved over the substrate pattern in terms feature size, shape, and uniformity, as well as regular spacing between arrays of features and between the features within each array compared to the substrate pattern. In certain embodiments, the density and total number of pattern features in the block copolymer film is also increased. High density and quality nanoimprint templates and other nanopatterned structures are also provided.

https://science.sciencemag.org/content/sci/321/5891/936.full.pdf

Density multiplication and improved lithography by directed block copolymer assembly

Directing the self-assembly of block copolymers

The nanometer-scale architectures in thin films of self-assembling block copolymers have inspired a variety of new applications. For example, the uniformly sized and shaped nanodomains formed in the films have been used for nanolithography, nanoparticle synthesis, and high-density information storage media. Imperative to all of these applications, however, is a high degree of control over orientation of the nanodomains relative to the surface of the film as well as control over order in the plane of the film. Induced fields including electric, shear, and surface fields have been demonstrated to influence orientation. Both heteroepitaxy and graphoepitaxy can induce positional order on the nanodomains in the plane of the film. This article will briefly review a variety of mechanisms for gaining control over block copolymer order as well as many of the applications of these materials. Particular attention is paid to the potential of perfecting long-range two-dimensional order over a broader range of length scales and the extension of these concepts to functional materials and more complex architectures.

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Patterning with block copolymer thin films

We combine a self-organizing diblock copolymer system with semiconductor processing to produce silicon capacitors with increased charge storage capacity over planar structures. Our process uses a diblock copolymer thin film as a mask for dry etching to roughen a silicon surface on a 30 nm length scale, which is well below photolithographic resolution limits. Electron microscopy correlates measured capacitance values with silicon etch depth, and the data agree well with a geometric estimate. This block copolymer nanotemplating process is compatible with standard semiconductor processing techniques and is scalable to large wafer dimensions.

Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication

Thin films of self-organizing diblock copolymers may be suitable for semiconductor applications since they enable patterning of ordered domains with dimensions below photolithographic resolution over wafer-scale areas. We investigate the process window for forming ordered arrays of nanoscale polymer domains in thin films across 8-in.-diam silicon wafers, including the effect of substrate material and surface treatment, annealing conditions, copolymer molecular weight, and film thickness. We also demonstrate pattern transfer of the nanoporous polymer template using both reactive ion etching and metal lift off.

Nanoscale patterning using self-assembled polymers for semiconductor applications

A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.

Fabrication process for a magnetic tunnel junction device

We combine nanometer-scale polymer self assembly with advanced semiconductor microfabrication to produce metal-oxide-semiconductor (MOS) capacitors with accumulation capacitance more than 400% higher than planar devices of the same lateral area The self assembly technique achieves this degree of enhancement using only standard processing techniques, thereby obviating additional process complexity These devices are suitable for use as on-chip power supply decoupling capacitors, particularly in high-performance silicon-on-insulator technology

High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors

A method for etching silicon is described incorporating first and second steps of reactive ion etching through a patterned oxide layer in respective atmospheres of HBr, Cl 2 and O 2 and then HBr and O 2 in situ by terminating the first etching step and removing substantially all Cl 2 before continuing with the second step of etching. The invention overcomes the problem of uneven etching of n+ and p+ silicon gates for CMOS transistor logic during the step of simultaneously etching silicon to form sub 0.25 micron gate lengths and vertical sidewalls while stopping on the gate oxide.

Keith Raymond Milkove

Papers

Integration of self-assembled diblock copolymers for semiconductor capacitor fabrication

Nanoscale patterning using self-assembled polymers for semiconductor applications

Fabrication process for a magnetic tunnel junction device

High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors

Silicon etching method