An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

▪ Abstract Semiconductor nanowires and nanotubes exhibit novel electronic and optical properties owing to their unique structural one-dimensionality and possible quantum confinement effects in two dimensions. With a broad selection of compositions and band structures, these one-dimensional semiconductor nanostructures are considered to be the critical components in a wide range of potential nanoscale device applications. To fully exploit these one-dimensional nanostructures, current research has focused on rational synthetic control of one-dimensional nanoscale building blocks, novel properties characterization and device fabrication based on nanowire building blocks, and integration of nanowire elements into complex functional architectures. Significant progress has been made in a few short years. This review highlights the recent advances in the field, using work from this laboratory for illustration. The understanding of general nanocrystal growth mechanisms serves as the foundation for the rational sy...

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Semiconductor nanowires and nanotubes

Methods to pattern substrates with dense periodic nanostructures that combine top-down lithographic tools and self-assembling block copolymer materials are provided. According to various embodiments, the methods involve chemically patterning a substrate, depositing a block copolymer film on the chemically patterned imaging layer, and allowing the block copolymer to self-assemble in the presence of the chemically patterned substrate, thereby producing a pattern in the block copolymer film that is improved over the substrate pattern in terms feature size, shape, and uniformity, as well as regular spacing between arrays of features and between the features within each array compared to the substrate pattern. In certain embodiments, the density and total number of pattern features in the block copolymer film is also increased. High density and quality nanoimprint templates and other nanopatterned structures are also provided.

https://science.sciencemag.org/content/sci/321/5891/936.full.pdf

Density multiplication and improved lithography by directed block copolymer assembly

Directing the self-assembly of block copolymers

The nanometer-scale architectures in thin films of self-assembling block copolymers have inspired a variety of new applications. For example, the uniformly sized and shaped nanodomains formed in the films have been used for nanolithography, nanoparticle synthesis, and high-density information storage media. Imperative to all of these applications, however, is a high degree of control over orientation of the nanodomains relative to the surface of the film as well as control over order in the plane of the film. Induced fields including electric, shear, and surface fields have been demonstrated to influence orientation. Both heteroepitaxy and graphoepitaxy can induce positional order on the nanodomains in the plane of the film. This article will briefly review a variety of mechanisms for gaining control over block copolymer order as well as many of the applications of these materials. Particular attention is paid to the potential of perfecting long-range two-dimensional order over a broader range of length scales and the extension of these concepts to functional materials and more complex architectures.

/pdf/patterning-with-block-copolymer-thin-films-5gldelhkf5.pdf

Patterning with block copolymer thin films

In this letter, we report self-aligned n-channel germanium (Ge) MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate electrode. Excellent off-state current is achieved through the reduction of junction leakage. For the first time, we have demonstrated an n-channel Ge MOSFET with a subthreshold slope of 150 mV/dec and an on-off current ratio of /spl sim/10/sup 4/.

Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate

Self-assembled diblock copolymer thin films are used as sacrificial layers for the transfer of dense nanoscale patterns into more robust materials. We detail the processes used to achieve highly uniform nanoporous dielectric films, high-aspect-ratio nanotextured silicon, silicon nitride dot arrays, silicon pillar arrays, and silicon tip arrays. All techniques are compatible with standard semiconductor fabrication processes. We also discuss the possible applications of each resulting nanometer-scale structure, including high surface area substrates for capacitors and biochips, quantum dot arrays for nonvolatile memories, and silicon pillar arrays for vertical transistors or field-emission displays.

Process integration of self-assembled polymer templates into silicon nanofabrication

We combine nanometer-scale polymer self assembly with advanced semiconductor microfabrication to produce metal-oxide-semiconductor (MOS) capacitors with accumulation capacitance more than 400% higher than planar devices of the same lateral area The self assembly technique achieves this degree of enhancement using only standard processing techniques, thereby obviating additional process complexity These devices are suitable for use as on-chip power supply decoupling capacitors, particularly in high-performance silicon-on-insulator technology

High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors

Integration of polymer self assembly with semiconductor processing enables sub-lithographic patterning of integrated circuit (IC) device elements and offers a non-traditional pathway to performance improvements (Black, 2005). We discuss target applications including surface-roughening for on-chip decoupling capacitors (Black et al., 2004), patterning nanocrystal floating gates for FLASH devices (Guarini et al., 2003), and defining FET channel arrays (Black, 2005)

Polymer self assembly in semiconductor microelectronics

At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.

E. Sikorski

Papers

Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate

Process integration of self-assembled polymer templates into silicon nanofabrication

High-capacity, self-assembled metal-oxide-semiconductor decoupling capacitors

Polymer self assembly in semiconductor microelectronics

FinFET performance advantage at 22nm: An AC perspective