An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Atomic-scale control and manipulation of the microstructure of polycrystalline thin films during kinetically limited low-temperature deposition, crucial for a broad range of industrial applications, has been a leading goal of materials science during the past decades. Here, we review the present understanding of film growth processes—nucleation, coalescence, competitive grain growth, and recrystallization—and their role in microstructural evolution as a function of deposition variables including temperature, the presence of reactive species, and the use of low-energy ion irradiation during growth.

Microstructural evolution during film growth

The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the character...

Low dielectric constant materials for microelectronics

The once-ephemeral radiation-induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation-induced charge. The soft error sensitivity as a function of technology scaling for various memory and logic components is then presented with a consideration of which applications are most likely to require soft error mitigation.

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Radiation-induced soft errors in advanced semiconductor technologies

As technology continues towards smaller, thinner and lighter devices, more stringent demands are placed on thin polymer films as diffusion barriers, dielectric coatings, electronic packaging and so on. Therefore, there is a growing need for testing platforms to rapidly determine the mechanical properties of thin polymer films and coatings. We introduce here an elegant, efficient measurement method that yields the elastic moduli of nanoscale polymer films in a rapid and quantitative manner without the need for expensive equipment or material-specific modelling. The technique exploits a buckling instability that occurs in bilayers consisting of a stiff, thin film coated onto a relatively soft, thick substrate. Using the spacing of these highly periodic wrinkles, we calculate the film's elastic modulus by applying well-established buckling mechanics. We successfully apply this new measurement platform to several systems displaying a wide range of thicknessess (nanometre to micrometre) and moduli (MPa to GPa).

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A buckling-based metrology for measuring the elastic moduli of polymeric thin films

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Low-Energy Proton Testing Using Cyclotrons Sources

A method of forming an electrical device is provided that includes forming microprocessor devices on a microprocessor die; forming memory devices on an memory device die; forming component devices on a component die; and forming a plurality of packing devices on a packaging die. Transferring a plurality of each of said microprocessor devices, memory devices, component devices and packaging components to a supporting substrate, wherein the packaging components electrically interconnect the memory devices, component devices and microprocessor devices in individualized groups. Sectioning the supporting substrate to provide said individualized groups of memory devices, component devices and microprocessor devices that are interconnected by a packaging component.

Heterogeneous miniaturization platform

Texture and Grain Structure Effects on the Reliability of Microelectronic Interconnects

Issues that are addressed in accordance with at least one presently preferred embodiment of the present invention, are: improvements upon the time it takes to physically swap degraders (done previously by hand); the safety involved in doing so, since the degraders become highly radioactive; possible improved energy resolution and beam stability if the accelerator can be left running continuously; and in-situ monitoring of beam current, beam position and stability. Particularly contemplated are methods and arrangements for changing degraders automatically, not manually, and in a safe manner.

Automatic exchange of degraders in accelerated testing of computer chips

PROBLEM TO BE SOLVED: To improve electromigration resistance of a copper electric conductor SOLUTION: Impurities which improve the electromigraion resistance are added to the copper electric conductor after copper composition is deposited on inside a holding place The impurities are C, O, C1, S and N, and a concentration level of the impurities is about 001ppm or about 1,000ppm The impurities are made by electroplating copper after copper seed is deposited on inside the holding place and ion is implanted, or by electrodepositing the copper composition including the impurities and diffusing the impurities inside the copper seed layer after the copper layer is deposited, or by implanting dopant ion after the deposition of a barrier layer and then depositing the copper seed layer Annealing is performed for diffusion After the copper electric conductor is planarized, at least one element is ion-implanted into these surface layers COPYRIGHT: (C)2004,JPO

Kenneth P. Rodbell

Papers

Low-Energy Proton Testing Using Cyclotrons Sources

Heterogeneous miniaturization platform

Texture and Grain Structure Effects on the Reliability of Microelectronic Interconnects

Automatic exchange of degraders in accelerated testing of computer chips

Method for forming copper electric conductor inside electron structure