K
Kerstin Schelm
Researcher at IBM
Publications - 21
Citations - 209
Kerstin Schelm is an academic researcher from IBM. The author has contributed to research in topics: Translation lookaside buffer & Adder. The author has an hindex of 5, co-authored 21 publications receiving 115 citations.
Papers
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Proceedings ArticleDOI
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling
Ankur Agrawal,Sae Kyu Lee,Joel Abraham Silberman,Matthew M. Ziegler,Mingu Kang,Swagath Venkataramani,Nianzheng Cao,Bruce M. Fleischer,Michael A. Guillorn,Matthew Cohen,Silvia Melitta Mueller,Jinwook Oh,Martin Lutz,Jinwook Jung,Siyu Koswatta,Ching Zhou,Vidhi Zalani,James J. Bonanno,Robert Casatuta,Chia-Yu Chen,Jungwook Choi,Howard M. Haynie,Alyssa Herbert,Radhika Jain,Monodeep Kar,Kyu-hyoun Kim,Li Yulong,Zhibin Ren,Scot H. Rider,Marcel Schaal,Kerstin Schelm,Michael R. Scheuermann,Xiao Sun,Hung Tran,Naigang Wang,Wei Wang,Xin Zhang,Vinay Velji Shah,Brian W. Curran,Vijayalakshmi Srinivasan,Pong-Fei Lu,Sunil Shukla,Leland Chang,Kailash Gopalakrishnan +43 more
TL;DR: In this article, a 4-core AI chip in 7nm EUV technology is presented to exploit cutting-edge algorithmic advances for iso-accurate models in low-precision training and inference to achieve leading-edge power-performance.
Patent
Translation lookaside buffer for virtual memory systems
TL;DR: The second level TLB is structured advantageously comprising two n-way set-associative sub-units of which one covers some higher level address translation levels and the other one, a lower level unit, covers some lower level translation level as mentioned in this paper.
Proceedings ArticleDOI
RaPiD: AI accelerator for ultra-low precision training and inference
Swagath Venkataramani,Vijayalakshmi Srinivasan,Wei Wang,Sanchari Sen,Jintao Zhang,Ankur Agrawal,Monodeep Kar,Shubham Jain,Alberto Mannari,Hoang Tran,Li Yulong,Eri Ogawa,Kazuaki Ishizaki,Hiroshi Inoue,Marcel Schaal,Mauricio J. Serrano,Jungwook Choi,Xiao Sun,Naigang Wang,Chia-Yu Chen,Allison Allain,James Bonano,Nianzheng Cao,Robert Casatuta,Matthew Cohen,Bruce M. Fleischer,Michael A. Guillorn,Howard M. Haynie,Jinwook Jung,Mingu Kang,Kyu-hyoun Kim,Siyu Koswatta,Sae Kyu Lee,Martin Lutz,Silvia Melitta Mueller,Jinwook Oh,Ashish Ranjan,Zhibin Ren,Scot H. Rider,Kerstin Schelm,Michael R. Scheuermann,Joel Abraham Silberman,Jie Yang,Vidhi Zalani,Xin Zhang,Ching Zhou,Matt Ziegler,Vinay Velji Shah,Moriyoshi Ohara,Pong-Fei Lu,Brian W. Curran,Sunil Shukla,Leland Chang,Kailash Gopalakrishnan +53 more
TL;DR: RaPiD1 as mentioned in this paper is a 4-core AI accelerator chip supporting a spectrum of precisions, namely, 16 and 8-bit floating-point and 4 and 2-bit fixed-point.
Proceedings ArticleDOI
The POWER7 Binary Floating-Point Unit
Maarten J. Boersma,Michael Kröner,Christophe Layer,Petra Leber,Silvia M. Müller,Kerstin Schelm +5 more
TL;DR: The binary Floating-Point Unit (FPU) of the POWER7 processor is a 5.5 cycle Fused Multiply-Add (FMA) design, fully compliant with the IEEE 754-2008 standard.
Patent
Method for sharing a translation lookaside buffer between CPUs
TL;DR: The TLB2 organization as discussed by the authors provides an interface to a major array, which is shared between the CPUs, for virtual-to-absolute address translation buffer (TLB 2).