Joel Abraham Silberman

TL;DR: A multi-TOPS AI core is presented for acceleration of deep learning training and inference in systems from edge devices to data centers by employing a dataflow architecture and an on-chip scratchpad hierarchy.

TL;DR: This 64 b single-issue integer processor, comprised of about one million transistors, is fabricated in a 0.15 /spl mu/m effective channel length, six-metal-layer CMOS technology and intended as a vehicle to explore circuit, clocking, microarchitecture, and methodology options for high-frequency processors.

TL;DR: The goal of the guTS project was to demonstrate that circuit techniques, and circuit-centric design, could significantly increase the performance of microprocessors, thus providing headroom for future performance growth beyond contributions from microarchitecture and CMOS technology.

TL;DR: In this article, a 4-core AI chip in 7nm EUV technology is presented to exploit cutting-edge algorithmic advances for iso-accurate models in low-precision training and inference to achieve leading-edge power-performance.

TL;DR: The design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBM's Austin Research Laboratory will cover design and verification tools as well as circuit constraints and microarchitecture philosophy.