Showing papers by "Kewal K. Saluja published in 1993"

A tutorial on built-in self-test. I. Principles

Abstract: An overview of built-in self-test (BIST) principles and practices is presented. The issues and economics underlying BIST are discussed, and the related hierarchical test structures are introduced. The fundamental BIST concepts of pattern generation and response analysis are explained. Linear feedback shift register theory is reviewed. >

A tutorial on built-in self-test. 2. Applications

Abstract: For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples. >

An efficient algorithm for sequential circuit test generation

Abstract: This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of Initial Timeframe Algorithm and correct implementation of a solution to the Previous State Information Problem. The Initial Timeframe Algorithm, one of the most important aspects of the test generator, determines the number of timeframes required to excite the fault for which a test is to be derived and the number of timeframes required to observe the excited fault. Correct determination of the number of timeframes in which the fault should be excited (activated) and observed saves the test generator from performing unnecessary search in the input space. Test generation is unidirectional, i.e., it is done strictly in forward time, and flip-flops in the initial timeframe are never assigned a state that needs to be justified later. The algorithm saves both the good and the faulty machine states after finding a test to aid in subsequent test generation. The Previous State Information Problem, which has often been ignored by existing test generators, is presented and discussed in the paper. Experimental results are presented to demonstrate the effectiveness of the algorithm. >

Theory, Analysis and Implementation of an On-LineBIST Technique

Abstract: A Built-ln Concurrent Self-Test (BICST) technique for testing combinational logic circuits concurrently with their normal operation is proposed. Concept of sharing the test hardware between identical circuits to reduce the overall area overhead is introduced. The method was implemented in the design of an ALU with on-line test capability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip area and it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increase in the size of the ALU.

Testing check bits at no cost in RAMs with on-chip ECC

Abstract: The paper addresses the problem of testing the check bits in RAMs with on-chip ECC. A solution is proposed in which the check bits are tested in parallel with the testing of the information bits. The solution entails finding a class of parity-check matrices that have the property that all the check bits can be tested for pattern-sensitive faults while the information bits are being tested, without any increase in the length of the test sequence. Further, the parity-check matrices are such that there is no loss in error-correction capabilities, and there is no penalty in the worst-case delay of the error-correcting logic.

Parallel computation of LFSR signatures

Abstract: Off-line determination of signatures (both good circuit and faulty circuits) for built-in self-test applications is a compute-intensive process that involves cycle-by-cycle simulation of the signature analyzer. In this paper, we present a parallel algorithm that can speed up the computation of (single input and multiple input) LFSR signatures by almost a factor of n, where n is the number of processors used. This parallel algorithm is designed by dividing that total number of time-frames to be simulated into partitions, and assigning each partition to a processor. Each processor determines the contribution of its partition to the final signature, and the contributions of different processors are merged, with very little effort, to obtain a single signature. The speedup given by our parallel algorithm is over and above any speedups provided by other sequential speedup techniques such as the use of lookup tables. We also present the results of a simulation study showing the speedup achieved by the parallel algorithm on a Sequent multiprocessor system. >

Efficient test vectors for ISCAS sequential benchmark circuits

Abstract: The sequential automatic test pattern generation system FASTEST is implemented with new heuristics to produce efficient test vectors for sequential circuits. The efficiency of FASTEST in terms of the quality of test vectors is demonstrated. The test vectors provide excellent fault coverage by fairly short test sequences. The profile of the ISCAS benchmark circuits is also described. >

An efficient algorithm for bipartite PLA folding

Abstract: Programmable logic arrays (PLAs) provide a flexible and efficient way of synthesizing arbitrary combinational functions as well as sequential logic circuits. They are used in both LSI and VLSI technologies. The disadvantage of using PLAs is that most PLAs are very sparse. The high sparsity of the PLA results in a significant waste of silicon area. PLA folding is a technique which reclaims unused area in the original PLA. This paper proposes a column bipartite folding algorithm based on matrix representation. Heuristics are used to reduce the search space and to speed up the search processes. The algorithm has been implemented in C programming language on a SUN-4 workstation. The program was used to study several large PLAs of varying sizes. The experimental results show that in most cases the proposed algorithm finds optimal solution in a reasonable CPU time. >

CCSTG: an efficient test pattern generator for sequential circuits

Abstract: A simple method which combines the efficiencies of an event driven implication method and speed of a compiled code implication is proposed for use in a sequential test pattern generator. This method, in conjunction with several other concepts and heuristics, is used to implement a sequential test pattern generator CCSTG based on the sequential test generation algorithm used in FASTEST. It is shown that the performance of a sequential test pattern generator improves substantially when methods proposed in this paper are incorporated in a test pattern generator. The authors verified this assertion by comparing the performances of test pattern generators, with and without these features, for ISCAS-89 benchmark sequential circuits. >