Showing papers in "IEEE Design & Test of Computers in 1993"
TL;DR: The authors present a software-oriented approach to hardware-software partitioning which avoids restrictions on the software semantics as well as an iterative partitioning process based on hardware extraction controlled by a cost function.
Abstract: The authors present a software-oriented approach to hardware-software partitioning which avoids restrictions on the software semantics as well as an iterative partitioning process based on hardware extraction controlled by a cost function. This process is used in Cosyma, an experimental cosynthesis system for embedded controllers. As an example, the extraction of coprocessors for loops is demonstrated. Results are presented for several benchmark designs. >
644Â citations
TL;DR: The authors demonstrate the feasibility of synthesizing heterogeneous systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met.
Abstract: As system design grows increasingly complex, the use of predesigned components, such as general-purpose microprocessors can simplify synthesized hardware. While the problems in designing systems that contain processors and application-specific integrated circuit chips are not new, computer-aided synthesis of such heterogeneous or mixed systems poses unique problems. The authors demonstrate the feasibility of synthesizing heterogeneous systems by using timing constraints to delegate tasks between hardware and software so that performance requirements can be met. System functionality is captured using the HardwareC hardware description language. The synthesis of an Ethernet-based network coprocessor is discussed as an example. >
556Â citations
TL;DR: The authors describe a systematic, heterogeneous design methodology using the Ptolemy framework for simulation, prototyping, and software synthesis of systems containing a mixture of hardware and software components.
Abstract: The authors describe a systematic, heterogeneous design methodology using the Ptolemy framework for simulation, prototyping, and software synthesis of systems containing a mixture of hardware and software components. They focus on signal-processing systems in which the hardware typically consists of custom data paths, finite-state machines (FSMs), glue logic and programmable processors. The software is one or more embedded programs running on the programmable components. >
301Â citations
TL;DR: A unified notation is presented for static random access memory (SRAM) fault models and fault tests for these models, and empirical results showing the fault coverage of the different test enable SRAM users to choose the fault models of interest as well as the test.
Abstract: A unified notation is presented for static random access memory (SRAM) fault models and fault tests for these models. The likelihood that the different types of faults will occur is demonstrated using inductive fault analysis and physical defect analysis. A set of march tests is discussed, together with methods to make composite tests for collections of fault tapes. Empirical results showing the fault coverage of the different test enable SRAM users to choose the fault models of interest as well as the test. >
288Â citations
TL;DR: An overview of built-in self-test (BIST) principles and practices is presented, and Linear feedback shift register theory is reviewed.
Abstract: An overview of built-in self-test (BIST) principles and practices is presented. The issues and economics underlying BIST are discussed, and the related hierarchical test structures are introduced. The fundamental BIST concepts of pattern generation and response analysis are explained. Linear feedback shift register theory is reviewed. >
280Â citations
TL;DR: A behavioral model of a class of mixed hardware-software systems is presented and a codesign methodology for such systems is defined.
Abstract: A behavioral model of a class of mixed hardware-software systems is presented. A codesign methodology for such systems is defined. The methodology includes hardware-software partitioning, behavioral synthesis, software compilation, and demonstration on a testbed consisting of a commercial central processing unit (CPU), field-programmable gate arrays, and programmable interconnections. Design examples that illustrate how certain characteristics of system behavior and constraints suggest hardware or software implementation are presented. >
280Â citations
TL;DR: The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed and testing approaches for general and structured logic, including ROMs, RAMs, and PLAs are described.
Abstract: For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples. >
207Â citations
TL;DR: SURF is a routing system designed specifically to meet the performance and cost constraints presented by today's packaging technologies, including thin-film multichip modules, and comes from its extremely flexible rubber-band data representation, which is an ideal framework for performance-driven and cost-driven routing.
Abstract: Current PCB (printed circuit board)-based routing tools cannot meet the performance and cost constraints presented by today's packaging technologies, including thin-film multichip modules. The authors describe SURF, a routing system designed specifically to meet these challenges. The strength of the SURF system comes from its extremely flexible rubber-band data representation. The rubber-band model is an ideal framework for performance-driven and cost-driven routing and naturally supports rectilinear, octilinear, and all-angle wiring patterns: one-and-a-half-layer routing; even wiring distribution; and powerful manual editing. The integrated spoke-based design-rule-checking/enforcement mechanism supports an incremental design style. As objects are moved or wires are resized, the wires are adjusted incrementally so that they maintain the same wiring topology. By working in the topological domain instead of the geometrical one, the designer can focus on higher-level design issues while the tool handles the precise geometrical details. >
110Â citations
TL;DR: A method of built-in self-diagnosis (BISD) for repairable, embedded static RAMs (SRAMs) is presented and the algorithms, hardware design, and design costs and tradeoffs are discussed.
Abstract: A method of built-in self-diagnosis (BISD) for repairable, embedded static RAMs (SRAMs) is presented. The BISD circuit, with self-repair, requires about 5% extra area in a 64-kb SRAM. The circuit contains a small reduced-instruction-set processor, which executes diagnosis algorithms stored in a ROM. These algorithms employ hybrid serial/parallel operations when external repair is available or modular operations when self-repair is required. The algorithms, hardware design, and design costs and tradeoffs are discussed. >
94Â citations
TL;DR: A rapid failure analysis method for high-density CMOS static RAMs (SRAMs) that uses realistic defect modeling and the results of functional and I/sub DDQ/ testing indicates that the method can efficiently debug the multimegabit-memory manufacturing process.
Abstract: A rapid failure analysis method for high-density CMOS static RAMs (SRAMs) that uses realistic defect modeling and the results of functional and I/sub DDQ/ testing is presented. The key to the method is the development of a defect-to-signature vocabulary through inductive fault analysis. Results indicate that the method can efficiently debug the multimegabit-memory manufacturing process. >
67Â citations
TL;DR: The authors detail the use of a target system simulator and a prototype printed circuit board (PCB) which facilitated a concurrent approach to the design of the hardware, software, and housing in the VuMan 1 project.
Abstract: The development of an embedded-computer system with a visual interface is described. The authors detail the use of a target system simulator and a prototype printed circuit board (PCB), which facilitated a concurrent approach to the design of the hardware, software, and housing. They outline this codesign process and illustrate its effects with comparative data from the earlier VuMan 1 project. >
TL;DR: It is shown that reasonable predictions are possible for functional tests, but that scan tests, due to misuse of theoretical equations, produce significantly worse quality levels than predicted.
Abstract: The use of stuck-at-fault coverage for estimating overall quality levels is examined. Data from a part tested with both functional and scan tests are analyzed and compared with quality predictions generated by three existing theoretical models. It is shown that reasonable predictions are possible for functional tests, but that scan tests, due to misuse of theoretical equations, produce significantly worse quality levels than predicted. >
TL;DR: A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented, in which a given path is tested by augmenting the netlist model of the circuit with a logic block.
Abstract: A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing. >
TL;DR: A memory test concept called the testing acceleration chip, which could reduce future test costs a hundredfold and yet maintain AC testing reliability, is presented.
Abstract: It is argued that the development of semiconductor memories has reached a turning point. In the multimegabit dynamic random access memories (DRAMs) of the future, major factors contributing to the chip cost are process complexity, die size, equipment cost, and test cost. If conventional test methods are used, test costs will grow at an especially rapid rate. A memory test concept called the testing acceleration chip, which could reduce future test costs a hundredfold and yet maintain AC testing reliability, is presented. >
TL;DR: The use of information flow models to conduct efficient fault isolation strategies to minimize some objective cost function and a technique that can include multiple cost criteria such as test time, skill level, and failure frequency is discussed.
Abstract: The use of information flow models to conduct efficient fault isolation strategies is described. Of particular concern is optimizing diagnosis to minimize some objective cost function. A technique that can include multiple cost criteria such as test time, skill level, and failure frequency, as well as information value, is discussed. >
TL;DR: A maximal k-color ordering is formulated for minimizing both interlayer and intralayer crosstalk as well as crossings in 3-D MCM substrates and a strategy that exhibits a good tradeoff between circuit performance and design cost is proposed.
Abstract: The authors describe the multilayer MCM (multichip module) routing problem, and propose an approach for routing high-performance MCMs with the objective of minimizing interconnect delays and crosstalk. They first introduce an approach for rapidly estimating the time-domain response of lossy transmission line trees, and propose a realistic second-order delay model for MCM interconnects. The delay model is used to guide a performance-driven global routing algorithm. Given the 2-D global paths, the next stage is layer assignment. An effective algorithm for constrained layer assignment is developed. Based on the best-known maxcut approximation algorithm (which performs well in practice), a maximal k-color ordering is formulated for minimizing both interlayer and intralayer crosstalk as well as crossings in 3-D MCM substrates. The authors also propose a strategy that exhibits a good tradeoff between circuit performance and design cost, instead of concentrating exclusively on a single objective such as area minimization. >
TL;DR: A procedure for estimating the complexity of synthesized designs from finite-state machine (FSM) specifications is described, and incorporating this estimate in the data path synthesis stage allows a trade-off between data path and control logic, resulting in high quality designs in terms of synthesize logic area.
Abstract: A procedure for estimating the complexity of synthesized designs from finite-state machine (FSM) specifications is described. Incorporating this estimate in the data path synthesis stage allows a trade-off between data path and control logic, resulting in high quality designs in terms of synthesized logic area. It is shown that the estimation process takes 650 to 3000 times less CPU time than the synthesis procedure. >
TL;DR: Three example applications of silicon-on-silicon multichip modules are discussed: a module used in a parallel processor, a low-cost silicon module for a high-volume consumer product application, and ahigh-performance digital telecommunications module.
Abstract: Three example applications of silicon-on-silicon multichip modules are discussed: a module used in a parallel processor, a low-cost silicon module for a high-volume consumer product application, and a high-performance digital telecommunications module. These applications illustrate the changes occurring in this technology and the forces that are driving these changes. >
TL;DR: The N2S schematic generator, which uses a variable-ordering technique in the initial placement phase and simple heuristics in the final placement phase, is described, which results in signal routing with minimal crossovers.
Abstract: The N2S schematic generator, which uses a variable-ordering technique in the initial placement phase and simple heuristics in the final placement phase, is described. Its channel-routing techniques result in signal routing with minimal crossovers. The authors demonstrate the efficiency of N2S by applying it to a set of benchmark sequential circuits. >
TL;DR: A methodology using a VHDL (VHSIC hardware description language) to create executable models of computer architectures independent of implementation attributes is described and such a model of a processor architecture known as the WM is presented.
Abstract: A methodology using a VHDL (VHSIC hardware description language) to create executable models of computer architectures independent of implementation attributes is described. The authors present such a model of a processor architecture known as the WM as the first step in developing an implementation. Simulations using the model can provide performance measurements such as potential parallelism. The model can also serve as an architectural specification for the computer. >
Journal Article•
TL;DR: The case study of an antitank missile ncher is presented in the context of a complete maintenance architecture and fault trees developed using an entropy-directed search process without modifications or constraints are discussed.
Abstract: Fault trees developed using an entropy-directed search process without modifications or constraints are discussed. To construct a fault tree using entropy-directed search, the computation load is reduced by determining which tests are not needed for diagnosis. The case study of an antitank missile ncher is presented in the context of a complete maintenance architecture. >
TL;DR: In CrossCheck, test structures are embedded into the ASIC base, rather than added by the designer to the schematic as with scan or built-in self-test (BIST) methodologies, which offers easier debugging and diagnostics methods to the designer.
Abstract: CrossCheck, an approach to the application-specific integrated circuit ASIC test problem that is based on embedding test structures into the base array of the ASIC, is discussed. With a specially designed storage element called the cross-controlled latch, CrossCheck combines controllability and observability to produce a highly testable ASIC having minimal area and performance overhead. CrossCheck is a designer-transparent solution that imposes none of the rules and restrictions of other design-for-testability (DFT) methodologies. In CrossCheck, test structures are embedded into the ASIC base, rather than added by the designer to the schematic as with scan or built-in self-test (BIST) methodologies. The built-in observability also offers easier debugging and diagnostics methods to the designer. Experimental results that demonstrate the potential of the CrossCheck method on a broad range of ASIC styles and sizes are presented. >
TL;DR: Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described, including an operating-voltage margin test.
Abstract: Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip VDC tuning technique that adjusts internal V/sub CC/ to compensate for the monitored characteristics of the process parameters during repair analysis testing. The second is an operating-voltage margin test, performed at various internal V/sub CC/ levels during the water sort test (WT) and the final shipping test (FT). >
TL;DR: Procedure 5012 of Mil-Std-883 describes requirements for the logic model, the assumed fault model and universe, fault classing, fault simulation and reporting of test results for digital microcircuits, and provides a consistent means of measuring fault coverage regardless of the specific logic and fault simulator used.
Abstract: Procedure 5012 of Mil-Std-883, which describes requirements for the logic model, the assumed fault model and universe, fault classing, fault simulation and reporting of test results for digital microcircuits is described. The procedure provides a consistent means of measuring fault coverage regardless of the specific logic and fault simulator used. Procedure 5012 addresses complex, embedded structures such as random-access memories (RAMs), read-only memories (ROMs), and programmable logic arrays (PLAs) weighting gate-level and non-gate-level structures by transistor counts to arrive at overall fault coverage. >
TL;DR: It is shown that extending the capability of an existing programming language is the simplest available technique for designing a PSL, and several useful high-level language constructs are proposed to facilitate modeling in order to have the simulation system deal with the low-level details transparently.
Abstract: The authors address several key issues in designing languages for parallel discrete-event simulation and survey the state-of-the-art techniques aimed at solving these problems. Attention is given to issues that are specific to parallel simulation, e.g., the parallel synchronization schemes, or issues that have not previously been a problem for sequential simulation, e.g., termination. Various specialized PSLs (parallel simulation languages) may also have quite different design issues. The problem of achieving transparency is addressed. In particular it is observed that a major difficulty in achieving the design criteria is the overhead introduced by the methods for solving the problems considered. In some cases making the design criteria less constrained appears to be unavoidable. The authors also propose several useful high-level language constructs to facilitate modeling in order to have the simulation system deal with the low-level details transparently. They show that extending the capability of an existing programming language is the simplest available technique for designing a PSL. >
TL;DR: To obtain a realistic fault model, the authors perform an inductive fault analysis on the DBM cells and show that the address generation method imposes different requirements on the test algorithms.
Abstract: Test algorithms for static double-buffered RAMs and pointer-addressed memories (PAMs) are presented. The reasons why test algorithms for single-buffered memories are inadequate to test double-buffered memories (DBMs) are discussed. To obtain a realistic fault model, the authors perform an inductive fault analysis on the DBM cells. They also show that the address generation method imposes different requirements on the test algorithms. >
TL;DR: The architecture and implementation of the Remote Interactive Scan Environment (RISE++), an object-oriented software system that makes use of distributed computing techniques, are discussed and can be used with other scan architectures.
Abstract: The architecture and implementation of the Remote Interactive Scan Environment (RISE++), an object-oriented software system that makes use of distributed computing techniques, are discussed. This system supports the development, application, and debugging of scan-based tests for the HP/Apollo Series 10000 RISC workstation and can be used with other scan architectures. RISE++ executes on a separate workstation and communicates with the system under test via a local area network. Test engineers can develop and debug scan tests under RISE++ because it tracks may trivial but important details for them and provides them with precise control over the test hardware. >
TL;DR: Results on two small-scale multiprocessor configurations show that the aliasing probability in analyzing signatures is comparable to that of an MLFSR but with fairly low area overhead; compared with the circular self-test path technique, less testing time is required by LTA.
Abstract: A novel test strategy, the Loop Testing Architecture (LTA), is introduced to reduce aliasing probability and testing time for multichip modules. This is accomplished by connecting cascadable built-in testers (CBITs) in neighboring pipelined stages to increase the length of the test suites. Fundamental properties of the LTA supporting randomness in the generated test patterns (state coverage) and the asymptotic aliasing probability are presented. Results on two small-scale multiprocessor configurations show that the aliasing probability in analyzing signatures is comparable to that of an MLFSR but with fairly low area overhead; compared with the circular self-test path technique, less testing time is required by LTA. Further evaluation of the potential capabilities provided by the LTA compared with boundary scan and other pipelined test scheduling approaches confirmed the usefulness of LTA as a framework for designing effective testable systems. >