Journal ArticleDOI
A tutorial on built-in self-test. I. Principles
TLDR
An overview of built-in self-test (BIST) principles and practices is presented, and Linear feedback shift register theory is reviewed.Abstract:
An overview of built-in self-test (BIST) principles and practices is presented. The issues and economics underlying BIST are discussed, and the related hierarchical test structures are introduced. The fundamental BIST concepts of pattern generation and response analysis are explained. Linear feedback shift register theory is reviewed. >read more
Citations
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Proceedings ArticleDOI
Efficient compression and application of deterministic patterns in a logic BIST architecture
TL;DR: The method presented achieves reductions of at least 100x in test data and 10x in tester cycles compared to deterministic ATPG while maintaining complete fault coverage, as confirmed by experimental results on industrial designs.
Journal ArticleDOI
Reliability- and process-variation aware design of integrated circuits.
TL;DR: A broad review the literature for Reliability- and Process-variation aware VLSI design shows a re-emergence of the topic as a core area of active research and is likely to be a part of any reliability qualification protocol for future technology generations.
Journal ArticleDOI
Test data decompression for multiple scan designs with boundary scan
TL;DR: An efficient scheme to compress and decompress in parallel deterministic test patterns for circuits with multiple scan chains while achieving a complete fault coverage for any fault model for which test cubes are obtainable is presented.
Journal ArticleDOI
Overview of Reliability Testing
TL;DR: This paper presents an overview of reliability testing, reliability estimation, and prediction models and approaches for the design of test plans which result in providing failure data and/or degradation data in a limited test duration.
Journal ArticleDOI
Testing systems on a chip
R. Chandramouli,S. Pateras +1 more
TL;DR: In this article, the development of fault-finding circuits built into ICs which will disclose defects in today's and tomorrow's block-based designs are examined, as well as their application in fault detection.
References
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Book
Shift register sequences
TL;DR: The Revised Edition of Shift Register Sequences contains a comprehensive bibliography of some 400 entries which cover the literature concerning the theory and applications of shift register sequences.
Book
Built In Test for VLSI: Pseudorandom Techniques
TL;DR: Digital Testing and the Need for Testable design Principles of Testable Design Pseudorandom Sequence Generators Test Response Compression Techniques and Limitations and Other Concerns of Random Pattern Testing Test System Requirements for Built-In Test Appendix References Index.
Journal ArticleDOI
Built-In Self-Test Techniques
TL;DR: The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.
Journal ArticleDOI
A data compression technique for built-in self-test
TL;DR: In this article, a data compression technique called self-testable and error-propagating space compression is proposed and analyzed, and the use of these gates in the design of self-testing and error propagating space compressors is discussed.