Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

Frontiers of silicon-on-insulator

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Semiconductor device and structure

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

Three dimensional device integration method and integrated device

A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.

Method for fabrication of a semiconductor device and structure

Low-temperature bonding of wafers has been studied utilizing reactive ion etching-mode plasma activation. The hydrophilic Si and thermally oxidized Si wafers were exposed to N 2 , Ar, or O 2 plasma prior to bonding in air or vacuum. After plasma treatment the wafers were cleaned in RCA-1 solution and/or deionized water. Strong bonding was achieved at 200°C with all the investigated plasma gases, if proper bonding and cleaning procedures were used. Extended RCA-I cleaning deteriorated the bond strength, but a short cleaning improved bonding. We found that the activation of the thermal oxide has a larger influence on the bond strength than the activation of the native oxide surface in Si/oxide wafer pairs. We suggest that the plasma treatment induces a highly disordered surface structure which enhances the diffusion of the water from the bonded interface. As a result of the plasma exposure the number of the surface OH groups is greatly increased enabling strong bonding at a low temperature.

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Effects of Plasma Activation on Hydrophilic Bonding of Si and SiO2

Mechanically induced layer transfer of single-crystal silicon by hydrogen ion implantation, low-temperature wafer bonding, and subsequent mechanical splitting of the implanted wafer has been investigated. The bond strength measurements using the crack opening method in room environment yield a surface energy of ⩾2000 mJ/m2 after exposure to oxygen plasma and subsequent hydrophilic silicon/silicon dioxide bonding at 200 °C. Mechanically induced layer transfer was carried out for silicon wafers implanted to a dose of 5×1016 H2/cm2 at 100 keV and annealed for 2 h at 200 °C. No feature was observed by atomic force microscopy (AFM) measurements on the unbonded free surface after this heat treatment. For lower doses of implantation, annealing at higher temperatures is required to enable the mechanical transfer. AFM measurements on the split silicon surface indicate that low-temperature wafer bonding and mechanical transfer yield a root mean square surface roughness of 4 nm which is less than in the standard Smart-Cut® process.

Mechanically induced Si layer transfer in hydrogen-implanted Si wafers

Single-crystalline silicon thin film on glass (cSOG) has been prepared using an "ion-cutting" based "layer-transfer" technique. Low-temperature processed thin-film transistors, fabricated both on cSOG and metal-induced laterally crystallized polycrystalline silicon, have been characterized and compared. The cSOG-based transistors performed comparatively better, exhibiting a significantly higher electron field-effect mobility (/spl sim/430 cm/sup 2//Vs), a steeper subthreshold slope and a lower leakage current that was also relatively insensitive to gate bias.

Characterization of low-temperature processed single-crystalline silicon thin-film transistor on glass

The strength of the H-implanted layer has been measured in 〈1 0 0〉 , 〈1 1 1〉 and 〈1 1 0〉 oriented Si wafers using the crack opening method. The required annealing temperature for mechanical layer transfer increases in the order 〈1 0 0〉 , 〈1 1 1〉 and 〈1 1 0〉 . The damage induced by the implantation has been studied by Rutherford backscattering in the channeling mode (RBS/C). The same methods have been used to investigate the influence of boron and arsenic doping on the mechanical exfoliation. Boron doping reduces the strength of the H-implanted layer thereby enabling mechanical layer transfer at temperatures below 200 °C. We found that the exfoliation takes place closer to the wafer surface in highly boron doped Si as compared to the undoped Si. The RBS damage peak also appears to move closer to the surface when the boron concentration of the H-implanted layer is >1019 cm−3. No lowering of the exfoliation temperature was observed for compensated and arsenic doped Si layers. We suggest that the lowering of the exfoliation temperature with increasing boron doping is related to Si–H bonds associated with the neutralization of shallow acceptors by hydrogen.

Cold ion-cutting of hydrogen implanted Si

Hydrogen ion-implantation into Si and subsequent heat treatment has been shown to be an effective means of cleaving thin layer of Si from its parent wafer. This process has been called Smart CutTM or ion-cut. We investigated the cleavage process in H-implanted silicon samples, in which the ion-cut was provoked thermally and mechanically, respectively. A 〈1 0 0〉 oriented p-type silicon wafer was irradiated at room temperature with 100 keV H2+-ions to a dose of 5 × 1016 H2/cm2 and subsequently joined to a handle wafer. Ion-cutting was achieved by two different methods: (1) thermally by annealing to 350 °C and (2) mechanically by insertion of a razor blade sidewise into the bonded wafers near the bond interface. The H-concentration and the crystal damage depth profiles before and after the ion-cut were investigated through the combined use of elastic recoil detection analysis and Rutherford backscattering spectroscopy (RBS). The location at which the ion-cut occurred was determined by RBS in channeling mode and cross-section transmission electron spectroscopy. The ion-cut depth was found to be independent on the cutting method. The gained knowledge was correlated to the depth distribution of the H-platelet density in the as-implanted sample, which contains two separate peaks in the implantation zone. The obtained results suggest that the ion-cut location coincides with the depth of the H-platelet density peak located at a larger depth.

Kimmo Henttinen

Papers

Effects of Plasma Activation on Hydrophilic Bonding of Si and SiO2

Mechanically induced Si layer transfer in hydrogen-implanted Si wafers

Characterization of low-temperature processed single-crystalline silicon thin-film transistor on glass

Cold ion-cutting of hydrogen implanted Si

Comparison of thermally and mechanically induced Si layer transfer in hydrogen-implanted Si wafers