Showing papers by "Laung-Terng Wang published in 2006"

VLSI Test Principles and Architectures: Design for Testability

Abstract: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. · Most up-to-date coverage of design for testability. · Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. · Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. · Lecture slides and exercise solutions for all chapters are now available. · Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website. Table of Contents Chapter 1 - Introduction Chapter 2 - Design for Testability Chapter 3 - Logic and Fault Simulation Chapter 4 - Test Generation Chapter 5 - Logic Built-In Self-Test Chapter 6 - Test Compression Chapter 7 - Logic Diagnosis Chapter 8 - Memory Testing and Built-In Self-Test Chapter 9 - Memory Diagnosis and Built-In Self-Repair Chapter 10 - Boundary Scan and Core-Based Testing Chapter 11 - Analog and Mixed-Signal Testing Chapter 12 - Test Technology Trends in the Nanometer Age

A new ATPG method for efficient capture power reduction during scan testing

Abstract: High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive JR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.

A Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation

Abstract: X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effectiveness of previous X-filling methods suffers from lack of guidance in selecting targets and values for X-filling. This paper addresses this problem with a highly-guided X-filling method based on two novel concepts: (1) X-score for X-filling target selection and (2) probabilistic weighted capture transition count for X-filling value selection. Experimental results show the superiority of the new X-filling method for capture power reduction.

Method and apparatus for broadcasting test patterns in a scan-based integrated circuit

Abstract: A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit. The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing

Abstract: The quality of at-speed testing is being severely challenged by the problem that an inter-clock logic block existing between two synchronous clocks is not efficiently tested or totally ignored due to complex test control. This paper addresses the problem with a novel inter-clock at-speed test control scheme, featuring a compact and robust on-chip inter-clock enable generator design. The new scheme can generate inter-clock at-speed test clocks from PLLs, and is feasible for both ATE-based scan testing and logic BIST. Successful applications to industrial circuits have proven its effectiveness in improving the quality of at-speed testing.

Test Data Compression Based on Clustered Random Access Scan

Abstract: We proposed a Clustered Random Access Scan (CRAS) architecture to reduce test data volume. CRAS makes use of the compatibility of the test stimuli to cluster the scan cells, and assigns every cluster a unique address. The compression ratio upper bound of CRAS is analyzed based on the random graph theory. Experimental results on ISCAS?89 benchmarks and two industry designs show that the proposed CRAS architecture can yield on average 67.3% reduction in test data volume, with reasonable area and routing overhead than scan design.

A Per-Test Fault Diagnosis Method Based on the X-Fault Model

Abstract: This paper proposes a new per-test fault diagnosis method based on the X-fault model. The X-fault model can represent all possible faulty behaviors of a physical defect or defects in a gate and/or on its fanout branches by assigning different X symbols assigned to the fanout branches. A partial symbolic fault simulation method is proposed for the X-fault model. Then, a novel technique is proposed for extracting more diagnostic information by analyzing matching details between observed and simulated responses. Furthermore, a unique method is proposed to score the results of fault diagnosis. Experimental results on benchmark circuits demonstrate the superiority of the proposed method over conventional per-test fault diagnosis based on the stuck-at fault model.

Logic Built-In Self-Test

Abstract: Publisher Summary Logic built-in self-test (BIST) is a design for testability (DFT) technique in whicha portion of a circuit on a chip, board, or system is used to test the digital logiccircuit itself. Logic BIST is crucial for many applications, in particular for lifecritical and mission-critical applications. These applications commonly found in the aerospace, automotive, banking, computer, healthcare, networking, and telecommunications industries require on-chip, on-board, or in-system self-test to improve the reliability of the entire system, as well as the ability to perform remote diagnosis. This chapter introduces the basic concepts and design rules of logic BIST. This chapter focuses on a number of test pattern generation and output response analysis techniques suitable for BIST implementations. Moreover, various BIST timing control diagrams are shown to illustrate how to test faults in a scan-based design containing multiple clock domains. Finally, the chapter demonstrates the process to design a logic BIST system comprised of a test pattern generator, output response analyzer, and logic BIST controller.

A New Method for Low-Capture-Power Test Generation for Scan Testing

Abstract: Research on low-power scan testing has been focused on the shift mode, with little consideration given to the capture mode power. However, high switching activity when capturing a test response can cause excessive IR-drop, resulting in significant yield loss due to faulty test results. This paper addresses this problem with a novel low-capture-power X-filling method by assigning 0's and 1's to unspecified bits (X-bits) in a test cube to reduce the switching activity in capture mode. This method can be easily incorporated into any test generation flow, where test cubes can be obtained during ATPG or by X-bit identification. Experimental results show the effectiveness of this method in reducing capture power dissipation without any impact on area, timing, and fault coverage.

Test Technology Trends in the Nanometer Age

Abstract: Publisher Summary This chapter presents several promising techniques to address some of the critical International technology roadmap for semiconductors (ITRS) needs and challenges for testing nanometer designs. The chapter briefly covers the techniques for delay testing; coping with physical failures, soft errors, and reliability issues; FPGA testing; MEMS testing; high-speed I or O testing; and RF testing. The semiconductor industry relies heavily on two test technologies: scan and built-in self-test (BIST). Scan is not sufficient because small feature size causes physical failures that are difficult to detect. BIST is also likely to cause problems if its low-fault-coverage problem is not soon solved. Therefore, it is imperative to seek viable test solutions. It presents test techniques with highly complex nanometer designs. The chapter also highlights that in the long term, 90%; of silicon will be embedded with BIST. Therefore, efforts should also be directed towards embedded software-based self-testing utilizing on-chip programmable resources.