M
Marc Guilmain
Researcher at Université de Sherbrooke
Publications - 9
Citations - 371
Marc Guilmain is an academic researcher from Université de Sherbrooke. The author has contributed to research in topics: Copper interconnect & Chemical-mechanical planarization. The author has an hindex of 6, co-authored 9 publications receiving 329 citations.
Papers
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Journal ArticleDOI
Three-Dimensional Electron Microscopy Simulation with the CASINO Monte Carlo Software
Hendrix Demers,Nicolas Poirier-Demers,Alexandre Réal Couture,Dany Joly,Marc Guilmain,Niels de Jonge,Dominique Drouin +6 more
TL;DR: The development of the 3D version of CASINO is presented, which has an improved energy range for scanning electron microscopy and scanning transmission electron microscopeopy applications and is available freely to the scientific community.
Journal ArticleDOI
SiO2 shallow nanostructures ICP etching using ZEP electroresist
TL;DR: In this article, an inductively coupled plasma (ICP) process was proposed to etch nanometer scale patterns defined by electron beam lithography in ZEP520A using a CF"4 based etching chemistry and a resist post-bake after development.
Journal ArticleDOI
A damascene platform for controlled ultra-thin nanowire fabrication.
TL;DR: A planarization end point detection method for metal nanostructures with adjustable thickness down to 2 nm is developed and the model adopted covers geometrical influences like oxidation and ageing.
Journal ArticleDOI
Tunnel Junction Engineering for Optimized Metallic Single-Electron Transistor
Khalil El Hajjam,Mohamed Amine Bounouar,Nicolas Baboux,Serge Ecoffey,Marc Guilmain,Etienne Puyoo,Laurent Francis,Abdelkader Souifi,Dominique Drouin,Francis Calmon +9 more
TL;DR: In this article, an engineered single-electron transistor (SET) based on multidielectric stacking was proposed to insure high-ON current, low-OFF current, and low capacitance.
Proceedings ArticleDOI
Single Electron Transistor analytical model for hybrid circuit design
Mohamed Amine Bounouar,Francis Calmon,A. Beaumont,Marc Guilmain,Wei Xuan,Serge Ecoffey,Dominique Drouin +6 more
TL;DR: A novel analytical and compact model of Single Electron Transistor developed and implemented in Verilog-A language for use in hybrid SET-CMOS logic circuit design has faithfully reproduced the behavior of metallic SET operating at room temperature.