International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

Global transition path search for dislocation formation in Ge on Si(001)

A method of forming a semiconductor structure includes providing a composite substrate, which includes a bulk silicon substrate and a silicon germanium (SiGe) layer over and adjoining the bulk silicon substrate. A first condensation is performed to the SiGe layer to form a condensed SiGe layer, so that the condensed SiGe layer has a substantially uniform germanium concentration. The condensed SiGe layer and a top portion of the bulk silicon substrate are etched to form a composite fin including a silicon fin and a condensed SiGe fin over the silicon fine. The method further includes oxidizing a portion of the silicon fin; and performing a second condensation to the condensed SiGe fin.

Germanium FinFETs having dielectric punch-through stoppers

Spin transistors are a new concept device that unites an ordinary transistor with the useful functions of a spin (magnetoresistive) device. They are expected to be a building block for novel integrated circuits employing spin degrees of freedom. The interesting features of spin transistors are nonvolatile information storage and reconfigurable output characteristics: these are very useful and suitable functionalities for various new integrated circuit architectures that are inaccessible to ordinary transistor circuits. This article reviews the current status and outlook of spin transistors from the viewpoint of integrated circuit applications. The device structure, operating principle, performance, and features of various spin transistors are discussed. The fundamental and key phenomena/technologies for spin injection, transport, and manipulation in semiconductors and the integrated circuit applications of spin transistors to nonvolatile logic and reconfigurable logic are also described.

Spin-Transistor Electronics: An Overview and Outlook

Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, the recent mobility enhancement technologies including application of strain and new channel materials such as SiGe, Ge and III–V materials are reviewed. These carrier transport enhancement technologies can be classified into three categories; global enhancement techniques, local enhancement techniques and global/local-merged techniques. We present our recent results on MOSFETs using these three types of the technologies with an emphasis on the global strained-Si/SiGe/Ge substrates and the combination with the local techniques. Finally, issues on device structures merged with III–V materials are briefly described.

Device structures and carrier transport properties of advanced CMOS using high mobility channels

We report a new microchannel epitaxy (MCE) technique for forming III–V semiconductor on insulator (III–V-OI) structures on a Si substrate with a thermally oxidized SiO2 mask for high performance n-type metal–insulator–semiconductor field-effect transistors (MISFETs). To reduce dislocations and antiphase domains (APDs), we propose a novel fabrication method of forming III–V-OI structures, where a two-step growth method is combined with MCE. The growth temperature of the low-temperature buffer layers and the growth rate in the two-step growth are optimized to meet the competing requirements for the reduction in APDs and selective growth. We demonstrate a fabrication of high-quality GaAs-OI structures using our proposed growth method under an optimized growth condition.

Masato Shichijo

Papers

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

Device structures and carrier transport properties of advanced CMOS using high mobility channels

Fabrication of III–V on Insulator Structures on Si Using Microchannel Epitaxy with a Two-Step Growth Technique

Formation of InGaAs-On-Insulator Structures by Epitaxial Lateral Over Growth from (111) Si

Fabrication of III-V-O-I (III-V on Insulator) structures on Si using micro-channel epitaxy with a two-step growth technique