Chemical vapour deposition is a promising route for large-scale graphene growth. It is now shown that—through the use of seeds—high-quality, large, single-crystal domains can be grown on a patterned arrangement, and can be used to carefully study the transport across grain boundaries.

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Control and characterization of individual grains and grain boundaries in graphene grown by chemical vapour deposition

The strong interest in graphene has motivated the scalable production of high quality graphene and graphene devices. Since large-scale graphene films synthesized to date are typically polycrystalline, it is important to characterize and control grain boundaries, generally believed to degrade graphene quality. Here we study single-crystal graphene grains synthesized by ambient CVD on polycrystalline Cu, and show how individual boundaries between coalescing grains affect graphene's electronic properties. The graphene grains show no definite epitaxial relationship with the Cu substrate, and can cross Cu grain boundaries. The edges of these grains are found to be predominantly parallel to zigzag directions. We show that grain boundaries give a significant Raman "D" peak, impede electrical transport, and induce prominent weak localization indicative of intervalley scattering in graphene. Finally, we demonstrate an approach using pre-patterned growth seeds to control graphene nucleation, opening a route towards scalable fabrication of single-crystal graphene devices without grain boundaries.

Control and Characterization of Individual Grains and Grain Boundaries in Graphene Grown by Chemical Vapor Deposition

The present invention provides device components geometries and fabrication strategies for enhancing the electronic performance of electronic devices based on thin films of randomly oriented or partially aligned semiconducting nanotubes. In certain aspects, devices and methods of the present invention incorporate a patterned layer of randomly oriented or partially aligned carbon nanotubes, such as one or more interconnected SWNT networks, providing a semiconductor channel exhibiting improved electronic properties relative to conventional nanotubes-based electronic systems.

Medium scale carbon nanotube thin film integrated circuits on flexible plastic substrates

We fabricate and characterize dual-gated graphene field-effect transistors (FETs) using Al2O3 as top-gate dielectric. We use a thin Al film as a nucleation layer to enable the atomic layer deposition of Al2O3. Our devices show mobility values of over 8,000 cm2/Vs at room temperature, a finding which indicates that the top-gate stack does not significantly increase the carrier scattering, and consequently degrade the device characteristics. We propose a device model to fit the experimental data using a single mobility value.

Realization of a High Mobility Dual-gated Graphene Field Effect Transistor with Al2O3 Dielectric

2.4. Block Copolymer Containing Hybrids 151 3. Block Copolymer Ordering in Thin Films 153 3.1. General Process Steps 153 3.2. Morphology of Thin Films 154 3.3. Thickness-Dependent Nanopatterning 154 3.3.1. Ultrathin Films: Monomolecular Films 155 3.3.2. Sub-L0 Thick Films 155 3.3.3. Thick Films 157 3.4. Placement Control: Directed Self-Assembly (DSA) 162 3.4.1. Topographic Guiding Patterns: Graphoepitaxy 163

Block copolymer based nanostructures: materials, processes, and applications to electronics.

(NOTE: Chapters 3-11 include an Introduction, Historical Development and Basic Concepts, Manufacturing Methods and Equipment, Measurement Methods, Models and Simulation, Limits and Future Trends in Technologies and Models, Summary of Key Ideas, References, and Problems.) 1. Introduction and Historical Perspective. Introduction. Integrated Circuits and the Planar Process-Key Inventions That Made It All Possible. Semiconductors. Semiconductor Devices. Semiconductor Circuit Families. Modern Scientific Discovery-Experiments, Theory and Computer Simulation. The Plan for This Book. 2. Modern CMOS Technology. CMOS Process Flow. 3. Crystal Growth, Wafer Fabrication and Basic Properties of Silicon Wafers. 4. Semiconductor Manufacturing- Clean Rooms, Wafer Cleaning and Gettering. 5. Lithography. 6. Thermal Oxidation and the Si/SiO2 Interface. 7. Dopant Diffusion. 8. Ion Implantation. 9. Thin Film Deposition. 10. Etching. 11. Backend Technology.

Silicon VLSI Technology: Fundamentals, Practice and Modeling

Ge on insulator (GOI) is desired to obtain metal-oxide-semiconductor transistors with high performance and low leakage current. We have developed a method to make GOI based on liquid-phase epitaxial (LPE) growth on Si substrates and a defect necking technique in which defects are confined to a very short distance. Self-aligned microcrucibles were used to hold the Ge liquid. High-quality single-crystal (100) as well as (111) oriented GOI structures were obtained with a process compatible with Si-based fabrication. No dislocations or stacking faults were found in the LPE Ge films on insulator. The orientation of the Ge crystals was controlled by the seeding Si substrate. This method opens up the possibility of integrating Ge device structures in a baseline Si integrated circuit process.

High-quality single-crystal Ge on insulator by liquid-phase epitaxy on Si substrates

For one-quarter/semester, senior/graduate level courses in Fabrication Processes. Unique in approach, this text provides an integrated view of silicon technology--with an emphasis on modern computer simulation. It describes not only the manufacturing practice associated with the technologies used in silicon chip fabrication, but also the underlying scientific basis for those technologies.

Silicon VLSI Technology

Systematic studies of the heteroepitaxial growth of germanium nanowires on silicon substrates were performed. These studies included the effect of sample preparation, substrate orientation, preanneal, growth temperature, and germane partial pressure on the growth of epitaxial germanium nanowires. Scanning electron microscopy and transmission electron microscopy were used to analyze the resulting nanowire growth. Germanium nanowires grew predominantly along the ⟨111⟩ crystallographic direction, with a minority of wires growing along the ⟨110⟩ direction, irrespective of the underlying silicon substrate orientation [silicon (111), (110), and (100)]. Decreasing the partial pressure of germane increased the number of ⟨111⟩ nanowires normal to the silicon (111) surface, compared to the other three available ⟨111⟩ directions. The growth rate of nanowires increased with the partial pressure of germane and to a lesser degree with temperature. The nucleation density of nanowire growth and the degree of epitaxy both...

Michael D. Deal

Papers

Silicon VLSI Technology: Fundamentals, Practice and Modeling

High-quality single-crystal Ge on insulator by liquid-phase epitaxy on Si substrates

Silicon VLSI Technology

Nature of germanium nanowire heteroepitaxy on silicon substrates

Microstructure of thermal hillocks on blanket Al thin films