An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor–liquid–solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs–Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.

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Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties

The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Tri-gate devices and methods of fabrication

Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

Semiconductor devices having a support structure for an active layer pattern and methods of forming the same

For better subthreshold swing (SS) and drain induced barrier lowering (DIBL) of FinFETs, the fin width is a more important parameter than the physical gate length. And it should be very thin and fully depleted. In this article, we introduce the fabrication of body-tied FinFETs with various fin widths, fabricated on bulk Si instead of SOI wafer, and propose a new gate length/fin width (L/sub g//W/sub fin/) criterion to get nearly ideal SS and DIBL for body-tied FinFETs. From experiments and simulations, it is proven that threshold voltage (V/sub th/) control is possible even under a 20 nm narrow fin width, and high performance FinFET operation is obtainable even under a 5 nm fin width.

Fin width scaling criteria of body-tied FinFET in sub-50 nm regime

A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

Methods of fabricating fin field transistors

Presented in this letter are the C-V data, measured from nanowire capacitors, which have been fabricated by connecting in parallel a large number of identically processed nanowire FETs. The C-V curves were examined over a range from accumulation to inversion with varying frequencies and at different electrode configurations. The gate response of the undoped and floating channel is investigated using C-V data, and the inversion charge and carrier mobility are accurately extracted by eliminating the effects of parasitic capacitances and series resistance Rsd. These observed data are compared with the data from planar MOS capacitor.

$C$ – $V$ Characteristics in Undoped Gate-All-Around Nanowire FET Array

We demonstrate for the first time high performance titanium nitride (TiN) single metal gate 65nm CMOS McFET (multichannel field effect transistor) SRAM cell transistor on bulk Si wafer. This single metal gate McFET shows suitable threshold voltage (VT) and excellent transistor characteristics of SS (sub-threshold swing) and DIBL (drain induced barrier lowering) with V/sub TN/ =+0.3V and V/sub TP/=-0.3V. The SRAM cell with this CMOS McFET, high static noise margin (SNM) of 350mV is achieved at 1.0V.

http://ieeexplore.ieee.org/iel5/9911/31516/01469265.pdf

Ming Li

Papers

Semiconductor devices having a support structure for an active layer pattern and methods of forming the same

Fin width scaling criteria of body-tied FinFET in sub-50 nm regime

Methods of fabricating fin field transistors

$C$ – $V$ Characteristics in Undoped Gate-All-Around Nanowire FET Array

Fully working high performance multi-channel field effect transistor (McFET) SRAM cell on bulk Si substrate using TiN single metal gate