(IEEE Transactions on Electron Devices,36(12):2816-2820)Field-Drifting Resonant Tunneling Through a-Si:H/a-Sil-xCx:H Quantum Wells at Different Locations of the i-Layer of a p-i-n Structure

Japanese Journal of Applied Physicsの創刊

The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

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Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs

Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field EI to increase the vertical breakdown voltage of a device VB,V are presented: 1) using a thin silicon layer with a high critical electric field ES,C ; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon epsivT, the formula of ES,C on silicon layer thickness tS is first obtained, which increases sharply with a decrease of tS, and reaches up to 141 V/mum at tS = 0.1 mum. Expressions for EI and VByV are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an EI value of 300 V/mum has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF.

Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

An ultralow specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) power lateral MOSFET is proposed. The MOSFET features double trenches: an oxide trench in the drift region and a trench gate extended to the buried oxide (BOX) (SOI DT MOSFET). First, the oxide trench causes multiple-directional depletion, which leads to electric field reshaping and an enhanced reduced surface field effect in the SOI layer. The electric field distributions in the SOI and BOX are thus improved. The oxide trench also increases the electric field strength in the x-direction due to the lower permittivity of oxide than that of Si. Both increase breakdown voltage (BV). Second, the trench makes the drift region folded in the y -direction, resulting in reduced cell pitch and Ron,sp. Third, the trench gate extended to the BOX further reduces Ron,sp by widening the vertical conduction area. The BV of the DT MOSFET increases from 91 V of the conventional SOI LDMOS to 233 V at a half-cell pitch of 6.5 μm, and the Ron,sp decreases from 5.1 to 3.3 mΩ·cm2.

Ultralow Specific On-Resistance High-Voltage SOI Lateral MOSFET

A junction-isolated triple RESURF (JITR) LDMOS with high breakdown voltage (BV) and low specific on-resistance (R
 on,sp
) is proposed in this letter. Compared with the conventional triple RESURF (CTR) LDMOS, the new structure features a highly doped n-type top (N-top) layer at the surface of N-well, providing a low on-resistance surface conduction path in the on-state. The experimental result demonstrates that low R
 on,sp
 and high BV of above 730 V are achieved by the JITR LDMOS. R
 on,sp
 of the JITR LDMOS is about 15%-24.3% lower than that of the CTR LDMOS. The JITR LDMOS with horizontal N-top layer and P-buried layer resembles a super junction (SJ) LDMOS. Compared with the reported SJ LDMOS, the SJ layer of JITR LDMOS is formed in the longitudinal direction instead of the width direction, and the proposed JITR LDMOS exhibits almost the highest BV and high power figure of merit (FOM, defined as BV
 2
/R
 on,sp
) in comparison to the published SJ LDMOS.

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

A novel superjunction (SJ) lateral double-diffused MOSFET (>950 V) with a thin layer SOI combining the advantage of low specific on-resistance ${R}_{\text {on,sp}}$ of the SJ and the high breakdown voltage ${V}_{\text {B}}$ of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably reduced ${R}_{\text {on,sp}}$ without sacrificing ${V}_{\text {B}}$ . Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field principle to carry out a high ${V}_{\text {B}}$ . The experimental results exhibit a ${R}_{\text {on,sp}}$ of 145 $\text{m}\Omega \cdot $ cm2 with a ${V}_{\text {B}}$ of 977 V. This represents a reduction in ${R}_{\text {on,sp}}$ by 18.1% when compared with the theoretical ${R}_{\text {on,sp}} \propto {V}_{\text {B}}^{{2.5}}\vphantom {^{^{^{^{}}}}}$ “silicon limit”.

Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

A novel high-voltage thin layer SOI technology based on 1-mum-thick silicon layer and 2-mum-thick buried oxide layer for driving color plasma display panels (PDP) has been developed. High-voltage pLDMOS with thick gate oxide, high- voltage nLDMOS, and low-voltage CMOS are compatible with LOCOS isolation. The proposed technology includes two aspects: first, an implantation after field oxide (IFO) technology is developed for achieving shallow junction depth of p-field region to avoid punch-through breakdown induced by back-gate (BG) effect of pLDMOS; second, conforming technology of isolation and oxidation is adopted for forming thick gate oxide of high-voltage pLDMOS, field oxide isolation of low-voltage CMOS, and full dielectric isolation between high-voltage and low-voltage CMOS simultaneously without additional mask and process. Compared with conventional technology of junction or trench isolation, the new high-voltage thin layer SOI technology achieves better process compatibility with lower process complexity and lower parasitic capacitance. A PDP data driver IC using the developed technology shows that the rise and fall times of the output stages are about 230 ns and 160 ns respectively under the supply voltage of 80 V and load capacitance of 50 pF.

High-Voltage Technology Based on Thin Layer SOI for Driving Plasma Display Panels

A novel 300-V high-side thin-layer-SOI field pLDMOS adopting field implant (FI) technology and multiple field plates (MFPs) has been developed. Breakdown mechanisms of back gate (BG) punchthrough and avalanche breakdown for highside thin-layer-SOI field pLDMOS are investigated by setting up an analytic model, simulating, and verifying experimentally. Shallow junction depth of p-field achieved by the proposed FI technology attenuates BG punchthrough effect; premature surface avalanche breakdown can be avoided by using MFPs. High-side field pLDMOS with a breakdown voltage (BV) of 340 V is experimentally realized on a 1.5-μm -thick SOI layer and successfully applied in a 200-V high-voltage switching IC.

Ming Qiao

Papers

Ultralow Specific On-Resistance High-Voltage SOI Lateral MOSFET

A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

High-Voltage Technology Based on Thin Layer SOI for Driving Plasma Display Panels

300-V High-Side Thin-Layer-SOI Field pLDMOS With Multiple Field Plates Based on Field Implant Technology