The k-means clustering algorithm is considered one of the most powerful and popular data mining algorithms in the research community. However, despite its popularity, the algorithm has certain limitations, including problems associated with random initialization of the centroids which leads to unexpected convergence. Additionally, such a clustering algorithm requires the number of clusters to be defined beforehand, which is responsible for different cluster shapes and outlier effects. A fundamental problem of the k-means algorithm is its inability to handle various data types. This paper provides a structured and synoptic overview of research conducted on the k-means algorithm to overcome such shortcomings. Variants of the k-means algorithms including their recent developments are discussed, where their effectiveness is investigated based on the experimental analysis of a variety of datasets. The detailed experimental analysis along with a thorough comparison among different k-means clustering algorithms differentiates our work compared to other existing survey papers. Furthermore, it outlines a clear and thorough understanding of the k-means algorithm along with its different research directions.

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The k-means Algorithm: A Comprehensive Survey and Performance Evaluation

Power semiconductor devices constitute the heart of modern power electronic apparatus. They are used in power electronic converters in the form of a matrix of on-off switches, and help to convert power from ac-to-dc (rectifier), dc-to-dc (chopper), dc-to-ac (inverter), and ac-to-ac at the same (ac controller) or different frequencies (cycloconverter). The switching mode power conversion gives high efficiency, but the disadvantage is that due to the nonlinearity of switches, harmonics are generated at both the supply and load sides. The switches are not ideal, and they have conduction and turn-on and turn-off switching losses. Converters are widely used in applications such as heating and lighting controls, ac and dc power supplies, electrochemical processes, dc and ac motor drives, static VAR generation, active harmonic filtering, etc. Although the cost of power semiconductor devices in power electronic equipment may hardly exceed 20–30 percent, the total equipment cost and performance may be highly influenced by the characteristics of the devices. An engineer designing equipment must understand the devices and their characteristics thoroughly in order to design efficient, reliable, and cost-effective systems with optimum performance. It is interesting to note that the modern technology evolution in power electronics has generally followed the evolution of power semiconductor devices. The advancement of microelectronics has greatly contributed to the knowledge of power device materials, processing, fabrication, packaging, modeling, and simulation. Today’s power semiconductor devices are almost exclusively based on silicon material and can be classified as follows:

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Power Semiconductor Devices

Solid State Electronics

The operation of switch-mode converters results in electromagnetic noise propagating throughout the power electronic system. Pulsewidth modulation (PWM) strategies with fixed switching frequency generate harmonics in the spectra of converter voltages and currents. Random PWM techniques allow the elimination of the harmonics, resulting in a continuous spectrum of noise, i.e., a spectrum retaining all frequency components. As a next step in advanced spectral shaping, a method presented in this paper produces spectral nulls at selected frequencies. This allows the carving of communication channels in the noise and the removal of spectral power at frequencies potentially harmful for the system. The theoretical analysis, computer simulations, implementation details, and experimental results are presented.

Shaping the Noise Spectrum in Power Electronic Converters

Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field EI to increase the vertical breakdown voltage of a device VB,V are presented: 1) using a thin silicon layer with a high critical electric field ES,C ; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon epsivT, the formula of ES,C on silicon layer thickness tS is first obtained, which increases sharply with a decrease of tS, and reaches up to 141 V/mum at tS = 0.1 mum. Expressions for EI and VByV are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an EI value of 300 V/mum has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF.

Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

A high-voltage lateral double-diffusion MOSFET (LDMOS) with a charge-balanced surface low on-resistance path (CBSLOP) layer is proposed and experimentally demonstrated using a modified CMOS process. The CBSLOP layer can not only provide a low on-resistance path in the on-state but also keep the charge balance between the N and P pillars of a surface low on-resistance path in the off-state, which results in improved breakdown voltage (BV). The experimental results show that the CBSLOP-LDMOS with a drift length of 35 mum exhibits a BV of 500 V and specific on-resistance (R on, sp) of 96 mOmega ldr cm2, yielding to a power figure of merit (BV 2/ R on, sp) of 2.6 MW/cm2 . The excellent device performances, coupled with a CMOS-compatible fabrication process, make the proposed CBSLOP-LDMOS a promising candidate for smart power integrated circuit.

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

A novel superjunction (SJ) lateral double-diffused MOSFET (>950 V) with a thin layer SOI combining the advantage of low specific on-resistance ${R}_{\text {on,sp}}$ of the SJ and the high breakdown voltage ${V}_{\text {B}}$ of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably reduced ${R}_{\text {on,sp}}$ without sacrificing ${V}_{\text {B}}$ . Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field principle to carry out a high ${V}_{\text {B}}$ . The experimental results exhibit a ${R}_{\text {on,sp}}$ of 145 $\text{m}\Omega \cdot $ cm2 with a ${V}_{\text {B}}$ of 977 V. This represents a reduction in ${R}_{\text {on,sp}}$ by 18.1% when compared with the theoretical ${R}_{\text {on,sp}} \propto {V}_{\text {B}}^{{2.5}}\vphantom {^{^{^{^{}}}}}$ “silicon limit”.

Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

Regulating dielectric genes of hollow metal-organic frameworks is a milestone project for microwave absorption (MA). However, there is still a bottleneck in deciphering the contribution of various dielectric genes, making it hard to expand the MA potential from selective encoding gene sequences. Herein, a custom-made proton tailoring strategy is used to build a controllable cavity, and meticulously designed thermodynamic regulation promotes the rearrangement of carbon atoms from disorder to order, thus enhancing the characteristics of charge transfer. Meanwhile, the defect-configuration transformation from heteroatom to vacancy and geometric configuration of hollow structure increase the polarization-related dielectric genes. Therefore, MA performance is enhanced towards broadband absorption (6.6 ​GHz, 1.78 ​mm) and high-efficiency loss (−62.5 ​dB), making samples suitable for complex open electromagnetic environments. This work realizes the tradeoff between dielectric gene sequences and provides a profound insight into the functions and sources of various microwave loss mechanisms. 

Selective coding dielectric genes based on proton tailoring to improve microwave absorption of MOFs

A new relationship between the specific ON-resistance $R_{\mathrm{\scriptscriptstyle ON}}$ and breakdown voltage $V_{B}$ for the balanced symmetric superjunction (SJ) device is presented to produce the lowest $R_{\mathrm{\scriptscriptstyle ON}}$ for a given $V_{B}$ . The design formulas, including the doping density NW and the drift length $L_{d}$ , are given for both the nonfull depletion (NFD) and the full depletion SJ devices with an introduction of the normalized $V_{B}$ factor $\eta $ . For the NFD SJ MOSFET, an $R_{\mathrm{\scriptscriptstyle ON}} \propto V_{B}^{1.03}$ relationship is obtained. The analytical results show good agreement with the numerical results.

Theory of Superjunction With NFD and FD Modes Based on Normalized Breakdown Voltage

Integrated in a 0.35 μm 700 V BCD process platform, ultra-low Ron, sp 700 V self-ISO (isolated) and NISO (non-isolated) DB-nLDMOS (dual P-buried-layer nLDMOS) are proposed in this paper. 800 V and 780 V are achieved for NISO and ISO DB-nLDMOS, of which Ron, sp are 11.5 Ω·mm2 and 11.2 Ω·mm2, respectively. Utra-low Ron, sp benefits from optimized device size and strict limitations for annealing temperature and time after P-bury-layer implantation. For ISO DB-nLDMOS, by separately implanting NWELLs, NWELL drift region of low doping concentration under gate poly is achieved and then premature avalanche breakdown around bird's beak is avoided. Moreover, a 600 V DB-nJFET (dual P-buried-layer nJFET) with innovative 3D pinch-off structure is also presented.

Zehong Li

Papers

High-Voltage LDMOS With Charge-Balanced Surface Low On-Resistance Path Layer

Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

Selective coding dielectric genes based on proton tailoring to improve microwave absorption of MOFs

Theory of Superjunction With NFD and FD Modes Based on Normalized Breakdown Voltage

A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS