An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The disclosure features apparatus, methods, and systems for wireless power transfer that include a power source featuring at least one resonator, a power receiver featuring at least one resonator, a first detector featuring one or more loops of conductive material and configured to generate an electrical signal based on a magnetic field between the power source and the power receiver, a second detector featuring conductive material, and control electronics coupled to the first and second detectors, where during operation, the control electronics are configured to measure the electrical signal of the first detector and compare the measured electrical signal of the first detector to baseline electrical information for the first detector to determine information about whether debris is positioned between the power source and the power receiver.

Foreign object detection in wireless energy transfer systems

(IEEE Transactions on Electron Devices,36(12):2816-2820)Field-Drifting Resonant Tunneling Through a-Si:H/a-Sil-xCx:H Quantum Wells at Different Locations of the i-Layer of a p-i-n Structure

A nitride semiconductor device includes: a first semiconductor layer made of first nitride semiconductor; a second semiconductor layer formed on a principal surface of the first semiconductor layer and made of second nitride semiconductor having a bandgap wider than that of the first nitride semiconductor; a control layer selectively formed on, or above, an upper portion of the second semiconductor layer and made of third nitride semiconductor having a p-type conductivity; source and drain electrodes formed on the second semiconductor layer at respective sides of the control layer; a gate electrode formed on the control layer; and a fourth semiconductor layer formed on a surface of the first semiconductor layer opposite to the principal surface, having a potential barrier in a valence band with respect to the first nitride semiconductor and made of fourth nitride semiconductor containing aluminum.

Nitride semiconductor device

A survey of Gallium Nitride HEMT for RF and high power applications

A novel silicon-on-insulator (SOI) high-voltage device structure with double-sided trenches on the buried oxide layer (DT SOI) is proposed and its breakdown characteristics are investigated theoretically and experimentally in this letter. Theoretically, the charges implemented in the DTs, whose density changes with the drain voltage, increase the electric field in the buried layer and modulate the electric field in the drift region, which results in the enhancement of the breakdown voltage (BV). Experimentally, the BV of 730 V is obtained for the first time in SOI LDMOS with DT on 20-mum SOI layer and 1- mum buried oxide layer

A Novel 700-V SOI LDMOS With Double-Sided Trench

A new SOI high voltage device structure with variable- k (permittivity) dielectric buried layer (VK SOI) is proposed in this paper. In this structure, the buried layer is made of two dielectrics, one of which is the low- k dielectric. The breakdown voltage is enhanced due to the modulation effect of the variable- k buried layer on the electric fields in the buried layer and drift region. An analytical model for the electric field and breakdown voltage in VK SOI is presented taking the modulation effect into account, from which the RESURF condition is derived. The dependences of the electric field distribution and breakdown voltage on the device parameters for VK SOI are investigated. Compared with the conventional SOI, the electric field of the buried layer and breakdown voltage of VK SOI with relative permittivity k I2  = 2 of the low- k dielectric are enhanced by 81% and 56%, respectively. The analytical results are in good agreement with those of 2D simulations. Finally, the proposed model and RESURF condition can be well applied to the conventional SOI and also extended to VT SOI (variable thickness buried layer SOI) devices.

A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

Based on the continuity theorem of electric displacement including interface charges, the enhanced dielectric layer field (ENDIF) for silicon-on-insulator (SOI) high-voltage devices is proposed. The following three approaches for enhancing the dielectric layer electric field EI to increase the vertical breakdown voltage of a device VB,V are presented: 1) using a thin silicon layer with a high critical electric field ES,C ; 2) introducing a low-permittivity dielectric buried layer; and 3) implementing interface charges between the silicon and the dielectric layer. Considering the threshold energy of silicon epsivT, the formula of ES,C on silicon layer thickness tS is first obtained, which increases sharply with a decrease of tS, and reaches up to 141 V/mum at tS = 0.1 mum. Expressions for EI and VByV are given, which agree well with simulative and experimental results. Based on the ENDIF, the new device structures are given, and an EI value of 300 V/mum has been experimentally obtained for double-sided trench SOI. Moreover, several conventional SOI devices are explained well by ENDIF.

Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

An ultralow specific on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) power lateral MOSFET is proposed. The MOSFET features double trenches: an oxide trench in the drift region and a trench gate extended to the buried oxide (BOX) (SOI DT MOSFET). First, the oxide trench causes multiple-directional depletion, which leads to electric field reshaping and an enhanced reduced surface field effect in the SOI layer. The electric field distributions in the SOI and BOX are thus improved. The oxide trench also increases the electric field strength in the x-direction due to the lower permittivity of oxide than that of Si. Both increase breakdown voltage (BV). Second, the trench makes the drift region folded in the y -direction, resulting in reduced cell pitch and Ron,sp. Third, the trench gate extended to the BOX further reduces Ron,sp by widening the vertical conduction area. The BV of the DT MOSFET increases from 91 V of the conventional SOI LDMOS to 233 V at a half-cell pitch of 6.5 μm, and the Ron,sp decreases from 5.1 to 3.3 mΩ·cm2.

Ultralow Specific On-Resistance High-Voltage SOI Lateral MOSFET

A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI) Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced Moreover, the Si window alleviates the self-heating effect The influences of the structure parameters on device characteristics are analyzed for the proposed device structure The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of EI > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 87 K in comparison with the conventional SOI and partial SOI devices

Xiaorong Luo

Papers

A Novel 700-V SOI LDMOS With Double-Sided Trench

A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon on Insulator

Ultralow Specific On-Resistance High-Voltage SOI Lateral MOSFET

New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI