A software-defined radio (SDR) receiver with baseband programmable RF bandpass filter (BPF) and complex impedance match is presented. The passive mixer-first architecture used here allows the impedance characteristics of the receiver's baseband circuits to be translated to the RF port of the receiver. Tuning the resistance at the baseband port allows for a real impedance match to the antenna. The addition of "complex feedback" between I and Q paths allows for matching to the imaginary component of the antenna impedance. By implementing both real and imaginary components with resistors in feedback around low noise baseband amplifiers, noise figure is also kept low. Tunable sampling capacitors on the baseband side of the passive mixer translate to tunable-Q filters on the RF port which allow for very good out-of-band linearity. Furthermore, the concept of in-band and out-of-band must be redefined as the impedance match and BPF center frequency move with the LO frequency, such that matching and filtering track the receive frequency. Additionally, 8-phase mixing is shown to provide significant benefits such as impedance matching range, rejection of blockers at LO harmonics, and lower noise figure (NF). Measurements from the receiver implemented in 65 nm CMOS show 70 dB of gain, NF as low as 3 dB, and 25 dBm out-of-band IIP3. Furthermore, tunable impedance matching shows that S11 <;- 30 dB can be achieved at any receive frequency from 0.1-1.3 GHz.

A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface

A differential single-port switched-RC N-path filter with band-pass characteristic is proposed. The switching frequency defines the center frequency, while the RC-time and duty cycle of the clock define the bandwidth. This allows for high-Q highly tunable filters which can for instance be useful for cognitive radio. Using a linear periodically time-variant (LPTV) model, exact expressions for the filter transfer function are derived. The behavior of the circuit including non-idealities such as maximum rejection, spectral aliasing, noise and effects due to mismatch in the paths is modeled and verified via measurements. A simple RLC equivalent circuit is provided, modeling bandwidth, quality factor and insertion loss of the filter. A 4-path architecture is realized in 65 nm CMOS. An off-chip transformer acts as a balun, improves filter-Q and realizes impedance matching. The differential architecture reduces clock-leakage and suppresses selectivity around even harmonics of the clock. The filter has a constant -3 dB bandwidth of 35 MHz and can be tuned from 100 MHz up to 1 GHz. Over the whole band, IIP3 is better than 14 dBm, P1dB=2 dBm and the noise figure is 3-5 dB, while the power dissipation increases from 2 mW to 16 mW (only clocking power).

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Tunable High-Q N-Path Band-Pass Filters: Modeling and Verification

A new wideband receiver architecture is proposed that employs two separate passive-mixer-based downconversion paths, which enables noise cancelling, but avoids voltage gain at blocker frequencies. This approach significantly relaxes the trade-off between noise, out-of-band linearity and wideband operation. The resulting prototype in 40 nm is functional from 80 MHz to 2.7 GHz and achieves a 2 dB noise figure, which only degrades to 4.1 dB in the presence of a 0 dBm blocker.

A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative ?iterative? harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and + 3.5 dBm in-band IIP3 while the out-of-band IIP3 is +16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > 60 dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply.

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Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Current analog harmonic rejection mixers typically provide 30-40 dB of harmonic rejection, which is often not sufficient. We present a mixed analog-digital approach to harmonic rejection mixing that uses a digital interference canceler to reject the strongest interferer. Simulations indicate that, given a practical RF scenario, the digital canceler is able to improve the signal-to-interference ratio by 30-45 dB.

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A Two-Stage Approach to Harmonic Rejection Mixing Using Blind Interference Cancellation

Wideband direct-conversion harmonic-rejection (HR) receivers for software-defined radio aim to remove or relax the pre-mixer RF filters, which are inflexible, bulky and costly [1,2]. HR schemes derived from [3] are often used, but amplitude and phase mismatches limit HR to between 30 and 40dB [1,2]. A quick calculation shows that much more rejection is wanted: in order to bring harmonic responses down to the noise floor (e.g. −100dBm in 10MHz for 4dB NF), and cope with interferers between −40 and 0dBm, an HR of 60 to 100dB is needed. Also in terrestrial TV receivers and in applications like DVB-H with co-existence requirements with GSM/WLAN transmitters in a small telephone, high HR is needed.

/pdf/a-400-to-900-mhz-receiver-with-dual-domain-harmonic-48iihfonic.pdf

A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation

Harmonic downmixing is an important effect that must be taken into account when performing sensitive spectrum sensing using direct-conversion receivers. When the local oscillator waveform contains harmonics of the fundamental frequency, the quadrature mixer in the receiver will downconvert RF signals found at these harmonics, termed harmonic images, in addition to the RF signals around the fundamental frequency. The harmonic images will be detected by power spectral density based sensing algorithms and will cause certain parts of the desired spectrum to be mistakenly flagged as occupied. Although harmonic downmixing is important to consider, it is an often negelected effect. This paper presents a harmonic rejection spectral sensing technique, that exploits two quadrature mixers. The mixers work with different LO frequencies, which decorrelate the harmonic images so that cross-correlation of their outputs renders an improved spectral estimate. In addition to rejecting the harmonic images, spurious signals entering the receiver through the analog baseband inputs was also be rejected. The frequency resolution of the spectral estimate is scalable and the rejection of the harmonic images increases 15 dB per 1000-fold increase of the correlation time. The complexity of the algorithm is analyzed and its performance is shown by means of simulations. The effect of I/Q imbalance is also taken into account.

/pdf/a-spectrum-sensing-technique-for-cognitive-radios-in-the-wylon0gw1j.pdf

A Spectrum Sensing Technique for Cognitive Radios in the Presence of Harmonic Images

We describe the design and evaluation of an integrated low-cost underwater sensor node designed for reconfigurability, allowing continuous operation on a relatively small rechargeable battery for one month. The node uses a host CPU for the network protocols and processing sensor data and a separate CPU performs signal processing for the ultrasonic acoustic software-defined Modulator/Demodulator (MODEM). A Frequency Shift Keying- (FSK-) based modulation scheme with configurable symbol rates, Hamming error correction, and Time-of-Arrival (ToA) estimation for underwater positioning is implemented. The onboard sensors, an accelerometer and a temperature sensor, can be used to measure basic environmental parameters; additional internal and external sensors are supported through industry-standard interfaces (I2C, SPI, and RS232) and an Analog to Digital Converter (ADC) for analog peripherals. A 433 MHz radio can be used when the node is deployed at the surface. Tests were performed to validate the low-power operation. Moreover the acoustic communication range and performance and ToA capabilities were evaluated. Results show that the node achieves the one-month lifetime, is able to perform communication in highly reflective environments, and performs ToA estimation with an accuracy of about 1-2 meters.

/pdf/proteus-ii-design-and-evaluation-of-an-integrated-power-2ug4stw0p3.pdf

N.A. Moseley

Papers

Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A Two-Stage Approach to Harmonic Rejection Mixing Using Blind Interference Cancellation

A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation

A Spectrum Sensing Technique for Cognitive Radios in the Presence of Harmonic Images

Proteus II: design and evaluation of an integrated power-efficient underwater sensor node