We have observed a darkening effect and the formation of permanent volume gratings in CdSSe semiconductor-doped glasses, both phenomena being certainly due to the same photochemical mechanism. This allowed us to reconcile contradictory results concerning the speed of their nonlinear response. We also studied the frequency dependence of X (3) below the gap and the intensity dependence of the reflectivity of these phase-conjugate mirrors. Our results can be interpreted in terms of the band-filling model with Boltzmann statistics. Finally, frequency- and. time-resolved luminescence measurements helped us to interpret various results.

New results on optical phase conjugation in semiconductor-doped glasses

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N 2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- ?m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 × 0.45 mm2. With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.

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A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The direct injection-locking scheme features wide locking ranges, a very low input capacitance, and highest frequency capability. The direct locking and the tradeoff between power consumption and tank quality factor is verified through three test circuits in 0.13-/spl mu/m standard CMOS, aiming at input frequency ranges of 50, 40, and 15 GHz. The 40- and 50-GHz dividers consume 3 mW with locking ranges of 80 MHz and 1.5 GHz. The 15-GHz divider consumes 23 mW and features a locking range of 2.8 GHz.

A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider

We develop a framework for analog-to-information conversion that enables sub-Nyquist acquisition and processing of wideband signals that are sparse in a local Fourier representation The first component of the framework is a random sampling system that can be implemented in practical hardware The second is an efficient information recovery algorithm to compute the spectrogram of the signal, which we dub the sparsogram A simulated acquisition of a frequency hopping signal operates at 33times sub-Nyquist average sampling rate with little degradation in signal quality

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Random Sampling for Analog-to-Information Conversion of Wideband Signals

Radio frequency integrated circuits (RFICs) are the building blocks that enable every device from cable television sets to mobile telephones to transmit and receive signals and data. This newly revised and expanded edition of the 2003 Artech House classic, "Radio Frequency Integrated Circuit Design", serves as an up-to-date, practical reference for complete RFIC know-how. The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results. By emphasizing working designs, this book practically transports readers into the authors' own RFIC lab so they can fully understand how these designs function. This title is suitable for radio frequency integrated circuit (RFIC) design engineers; radio systems architects; researchers and developers of RFIC technology; and, graduate level electrical engineering students.

Radio Frequency Integrated Circuit Design

The use of bang-bang phase-locked loops (BBPLLs) has become increasingly common in a lot of communications systems, in particular in the area of clock and data recovery. Although most of the BBPLLs implemented up to now use analog loop filters, the binary output of the phase detector naturally lends itself to a digital implementation. In this paper, the nonlinear dynamics of first- and second-order digital BBPLLs is analyzed from a design perspective. In particular, the effects of loop delays on the PLL performances are emphasized. Conditions for the existence of orbits (limit cycles) are derived, and the timing jitter performances are evaluated. Finally, useful expressions for the design and optimization of the PLL parameters for low jitter are given.

A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs

In this work, the effect of sampling clock jitter on the SNR of an analog-to-digital (AD) conversion is investigated from a practical perspective. Aperture jitter analyses have been dealing up to now with white spectrum jitter. This assumption does not hold for the output of phase-locked loops (PLL)-like frequency synthesizers, where the spectrum is shaped by the loop transfer function. Based on a linear approximation, a powerful expression for the SNR is derived, applicable to a jitter process with a generic autocorrelation function and generic input signal. A lot of different definitions of jitter are available in the literature; this work addresses also the problem of identifying correctly among them the "effective" jitter for a given SNR. This can be profitably used in the specification as well as verification of the jitter requirements of a frequency synthesizer used as sampling clock generator in the AD converter systems. The results have been checked through numerical simulation.

On the jitter requirements of the sampling clock for analog-to-digital converters

In the last few years, several digital implementations of phase-locked loops (PLLs) have emerged, in some cases outperforming analog ones. Some of these PLLs use a bang-bang phase detector to convert the phase error into a digital value. Unfortunately, that introduces a hard nonlinearity in the loop which prevents the use of the traditional linear analysis. Nevertheless, authors resort to linearized models for the noise analysis of this kind of loops, but to the author's knowledge, no attempt has been made to evaluate the limits of this approach. In this paper, we address the problem of investigating the limits of the linearized approach, and we apply it to the computation of the jitter transfer and the jitter generation depending on the level of noise at the binary phase detector input. The results will be compared to phase noise measurements obtained from a digital bang-bang PLL implemented in 130-nm CMOS technology.

Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation

Due to the presence of a binary phase detector (BPD) in the loop, bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems. Since the BPD is usually also the only nonlinear element in the loop, in practical applications, BBPLLs are commonly analyzed by first linearizing the BPD and then using the traditional mathematical techniques for linear systems. To the author's knowledge, in the literature, the gain of the linearized BPD (Kbpd) is determined neglecting the effect of the BBPLL dynamics on the effective jitter seen by the BPD. In this brief, we develop an approach to the determination of Kbpd which takes into consideration also this effect. The approach is based on modeling the dynamics of a BBPLL as a Markov chain. This approach gives new insights into the behavior of the BBPLL and leads to an expression for the Kbpd, which is more general than the one currently known in literature

Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs

We present a low-jitter digital LC phase-locked loop (PLL) in a standard digital 130-nm CMOS technology, aiming at, but not limited to, clock multiplication in high-speed digital serial interface transceivers. The PLL features a fully digital core and a digitally controlled LC oscillator. The use of an integrated programmable coil enables triple-band operation in multi-GHz range (2.2, 3.4, and 4.6 GHz) on a die area as small as 0.21 mm/sup 2/. A new architecture is proposed which improves the authors' previous work and allows to achieve an outstanding long-term jitter lower than 650 fs over the whole frequency range. The PLL consumes 13 mA of current at 1.5-V supply. Its performances compete favorably with the most advanced analog PLLs and are ahead of digital PLLs. Its digital nature makes it easily realizable in the mainstream digital CMOS technologies, robust against noise, and thus ideal for application as a low-jitter clock multiplying unit in digital intensive systems on chip.

N. Da Dalt

Papers

A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs

On the jitter requirements of the sampling clock for analog-to-digital converters

Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation

Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS