Journal ArticleDOI
MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
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TLDR
The MorphoSys architecture is described, including the reconfigurable processor array, the control processor, and data and configuration memories, and the suitability of MorphoSy for the target application domain is illustrated with examples such as video compression, data encryption and target recognition.Abstract:
This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems.read more
Citations
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Book ChapterDOI
ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix
TL;DR: A novel architecture with tightly coupled very long instruction word (VLIW) processor and coarse-grained reconfigurable matrix is proposed, which has good performance and is very compiler-friendly.
Book
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Scott Hauck,André DeHon +1 more
TL;DR: This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology.
Proceedings ArticleDOI
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory
TL;DR: The hardware architecture and software scheduling and partitioning techniques for TETRIS, a scalable NN accelerator using 3D memory, are presented and it is shown that despite the use of small SRAM buffers, the presence of3D memory simplifies dataflow scheduling for NN computations.
Journal ArticleDOI
Reconfigurable computing: architectures and design methods
Tim Todman,George A. Constantinides,Steven J. E. Wilton,Oskar Mencer,Wayne Luk,Peter Y. K. Cheung +5 more
TL;DR: It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.
Journal ArticleDOI
System-on-Chip: Reuse and Integration
Resve A. Saleh,Steven J. E. Wilton,Shahriar Mirabbasi,Alan J. Hu,Mark R. Greenstreet,Guy G.F. Lemieux,Partha Pratim Pande,C. Grecu,Andre Ivanov +8 more
TL;DR: This paper focuses on the reuse and integration issues encountered in this paradigm shift in system-on-chip (SoC) design, which includes connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network- on- chip (NoC) architectures.
References
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Proceedings Article
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